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2013 18th IEEE European Test Symposium (ETS)最新文献

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Adaptive quality binning for analog circuits 模拟电路的自适应质量分组
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569357
E. Yilmaz, S. Ozev, K. Butler
{"title":"Adaptive quality binning for analog circuits","authors":"E. Yilmaz, S. Ozev, K. Butler","doi":"10.1109/ETS.2013.6569357","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569357","url":null,"abstract":"Manufactured devices have a diverse performance/quality profile due to process variations. Devices with superior performance and quality are of higher value while the rest can be sold for a lower price. Separating manufactured devices according to their performance is defined as quality/performance binning and is a very effective way of lowering average device cost. In this manner, devices that have below average quality are not wasted and therefore device cost is reduced. Quality binned devices share the same design and typically go through the same manufacturing process and even the same test process. After the testing step, they are binned according to different sets of performance criteria, typically according to the customer specifications. The bin a device falls depends on the process and typically does not match the amount requested by the customers because of uncertainty (variation) of the process. In this work, we present a multi-bin quality-oriented adaptive test method that efficiently classifies the devices according to the desired quality criteria and minimizes the overall test time.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131088337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hybrid 3D pre-bonding test framework design 混合三维预粘接试验框架设计
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569388
Unni Chandran, Dan Zhao, Rathish Jayabharathi
{"title":"Hybrid 3D pre-bonding test framework design","authors":"Unni Chandran, Dan Zhao, Rathish Jayabharathi","doi":"10.1109/ETS.2013.6569388","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569388","url":null,"abstract":"We have proposed in this paper a hybrid wireless test framework for pre-bond testing of 3D-SICs. This framework exploits high data rate & low noise near field inductive coupling mechanism for test data transfer. Test stimuli for IP cores and test control for TSV BIST are wirelessly transmitted through the probe card. Test responses from IP cores and TSV BIST are relayed back to the probe card by WiPads. A scheduling heuristic was further proposed for parallel testing of TSVs and IP cores, achieving reasonably close testing times to LB.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On combining alternate test with spatial correlation modeling in analog/RF ICs 模拟/射频集成电路中交替测试与空间相关建模相结合的研究
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569358
K. Huang, Nathan Kupp, J. Carulli, Y. Makris
{"title":"On combining alternate test with spatial correlation modeling in analog/RF ICs","authors":"K. Huang, Nathan Kupp, J. Carulli, Y. Makris","doi":"10.1109/ETS.2013.6569358","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569358","url":null,"abstract":"Statistical intra-die correlation has been extensively studied as a means for reducing test cost in analog/RF ICs. Generally known as alternate test, this approach seeks to predict the performances of an analog/RF chip based on low-cost measurements on the same chip and statistical models learned from a training set of chips. Recently, an orthogonal direction for leveraging statistical correlation towards reducing test cost of analog/RF ICs has also gained traction. Specifically, inter-die spatial correlation models learned from specification tests on a sparse subset of die on a wafer are used to predict performances on the unobserved die. In this work, we investigate the potential of combining these two statistical approaches, anticipating that the performance prediction accuracy of the joint correlation model will surpass the accuracy of its constituents. Experimental results on industrial semiconductor manufacturing data validate this conjecture and corroborate the utility of the combined performance prediction models.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers 具有嵌入式核心和多塔的3d - sic的自动DfT插入和测试生成
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569350
C. Papameletis, B. Keller, V. Chickermane, E. Marinissen, S. Hamdioui
{"title":"Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers","authors":"C. Papameletis, B. Keller, V. Chickermane, E. Marinissen, S. Hamdioui","doi":"10.1109/ETS.2013.6569350","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569350","url":null,"abstract":"Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129841944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing 高速扫描测试中动态电源降噪的一种可感知布局的x填充方法
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569356
S. Kiamehr, F. Firouzi, M. Tahoori
{"title":"A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing","authors":"S. Kiamehr, F. Firouzi, M. Tahoori","doi":"10.1109/ETS.2013.6569356","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569356","url":null,"abstract":"Power Supply Noise (PSN) has emerged as an important resilience issue in nano-scale CMOS technology. Due to simultaneous switching of various gates, the actual supply voltage seen by individual gates inside the circuit might be lower than the nominal supply voltage, leading to extra delays. Since in at-speed scan testing simultaneous switchings are higher than the functional mode, test invalidation due to excessive PSN can happen, which may impact yield loss. In this paper, we propose a Linear Programming-based X-filling approach to minimize PSN in at-speed scan test by assigning appropriate values to X-bits in partially specified test patterns. In this paper, spatial and transition time correlations due to circuit layout, power mesh, and netlist are taken into account to increase the accuracy of dynamic PSN estimation and for the first time the delay of the circuit is directly targeted to minimize the effect of PSN during the at-speed scan test.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"272 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114242895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Test generation for circuits with embedded memories using SMT 测试生成电路与嵌入式存储器使用SMT
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569390
S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram
{"title":"Test generation for circuits with embedded memories using SMT","authors":"S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram","doi":"10.1109/ETS.2013.6569390","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569390","url":null,"abstract":"One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Bias temperature instability analysis in SRAM decoder SRAM解码器的偏置温度不稳定性分析
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569381
Seyab Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor
{"title":"Bias temperature instability analysis in SRAM decoder","authors":"Seyab Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor","doi":"10.1109/ETS.2013.6569381","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569381","url":null,"abstract":"In nanoscale era, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) weaken PMOS and NMOS transistors, respectively, leading to performance degradation. This paper presents a comprehensive analysis of NBTI and PBTI impacts on SRAM decoders including single stage static and dynamic as well as two stage static decoders while applying realistic addressing schemes (i.e. linear, gray and address complement) to present different workloads. The analysis shows that the strength of the impact strongly depends on the decoder design and the addressing scheme; the impact can be as worst as 28% additional delay in the activation of the wordline.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion OFDM发射机中EVM的分析建模，包括IIP3、I/Q不平衡、噪声、AM/AM和AM/PM失真的影响
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569361
A. Nassery, S. Ozev, M. Slamani
{"title":"Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion","authors":"A. Nassery, S. Ozev, M. Slamani","doi":"10.1109/ETS.2013.6569361","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569361","url":null,"abstract":"In this paper, we present a method for accurately calculating the Error Vector Magnitude (EVM) of OFDM transmitters based on their IQ mismatch, IIP3, noise, AM/AM and AM/PM distortion. The effects of these impairments are correlated. Thus, modeling and analyzing them in isolation results in large errors. We derive the analytical relation of the received symbol when all types of impairments are present at once and compute EVM based on this overall relation. This method helps test engineers to compute the EVM based on already measured parameters and eliminates the need to develop and set-up EVM measurements. Simulations and hardware measurements show that this calculation can be done with less than 1% error for a large range of EVM values. This error level has been shown to be within the uncertainty bounds of EVM measurements.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123183331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A minimum MSE sensor fusion algorithm with tolerance to multiple faults 一种具有多故障容忍度的最小MSE传感器融合算法
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569380
O. Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, K. Radecka
{"title":"A minimum MSE sensor fusion algorithm with tolerance to multiple faults","authors":"O. Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, K. Radecka","doi":"10.1109/ETS.2013.6569380","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569380","url":null,"abstract":"Sensor data fusion is a common approach to provide accurate and fault-tolerant sensor readouts in a multisensor system. This paper proposes an efficient data fusion algorithm using convex optimization for a multi-sensor system with given post-calibration statistical characteristics. A preprocessing step called screening is proposed to quickly detect multiple faulty sensors and exclude them from the fusion. Experimental results are evaluated on temperature sensors.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124039443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information 一种利用捕获周期功率信息增强诊断分辨率的算法
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569384
S. Potluri, Satya Trinadh, Roopashree Baskaran, N. Chandrachoodan, V. Kamakoti
{"title":"PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information","authors":"S. Potluri, Satya Trinadh, Roopashree Baskaran, N. Chandrachoodan, V. Kamakoti","doi":"10.1109/ETS.2013.6569384","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569384","url":null,"abstract":"Conventional ATPG tools help in detecting only the equivalence class to which a fault belongs and not the fault itself. This paper presents PinPoint, a technique that further divides the equivalence class into smaller sets based on the capture power consumed by the circuit under test in the presence of different faults in it, thus aiding in narrowing down on the fault. Applying the technique on ITC benchmark circuits yielded significant improvement in diagnostic resolution.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125981221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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