测试生成电路与嵌入式存储器使用SMT

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI:10.1109/ETS.2013.6569390

S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram

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引用次数: 3

摘要

测试现代soc的重要挑战之一是小型嵌入式存储器的存在。这些内存太小，无法使用内存BIST。此外，使这些嵌入式内存可扫描或使用MBIST将增加面积开销和/或测试应用程序时间。

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Test generation for circuits with embedded memories using SMT

One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time.

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来源期刊

2013 18th IEEE European Test Symposium (ETS)

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