Reconciling the IC test and security dichotomy

O. Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, R. Karri, Yier Jin, K. Huang, Y. Makris
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引用次数: 28

Abstract

Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.
协调IC测试和安全二分法
许多设计公司负担不起拥有和收购昂贵的代工厂,因此,他们选择无晶圆厂,并将设计制造外包给可能不值得信任的代工厂。集成电路(IC)设计流程的全球化带来了安全漏洞。如果设计是在不受(无晶圆厂)设计公司直接控制的代工厂制造的,那么逆向工程、恶意电路修改和知识产权(IP)盗版都是可能的。在本教程中,我们将通过与VLSI测试的联系来详细说明这些和类似的硬件安全威胁。我们将介绍基于信任的设计技术,如逻辑加密、老化加速攻击和有助于识别特洛伊木马和伪造ic的统计方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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