Robust optimization of test-architecture designs for core-based SoCs

Today's technology allows for the integration of many cores in a single die, for instance, in core-based SoCs, and an even larger number of cores are likely to be integrated over multiple layers in a 3D stack. In order to minimize test cost, the test architecture in a core-based SOC is optimized for minimum test time. Optimization methods in use today assume that all relevant input parameters, such as core test time and power consumption during test, are known at the design stage. However, these parameters can change after manufacturing and, in that scenario, the originally designed test architecture may no longer be optimal. Moreover, conventional optimization methods have to consider worst-case estimates for all input parameters to ensure feasibility, which can result in conservative and hence expensive solutions. We propose the use of robust optimization for test-architecture design and test scheduling. This goal of this approach is to find a solution that remains close to optimal in the presence of parameter variations. Experimental results for the ITC'02 SoC benchmarks show that, compared to optimization methods that target only a single point in the input-parameter space, robust optimization can better optimize test time in the presence of parameter variations.