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Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs 应力技术对90nm以下SOI cmosfet器件性能和可靠性的影响
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563553
W. Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang, W. Shiau
{"title":"Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs","authors":"W. Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang, W. Shiau","doi":"10.1109/SOI.2005.1563553","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563553","url":null,"abstract":"In this work, for 90nm PD-SOI CMOSFETs on <100> Si substrate, the impacts of high tensile stress GC liner-SiN thicknesses on device performance and hot-carrier induced degradations were investigated. For nMOSFETs, devices with 700A GC liner-SiN possess apparent mobility enhancement and hot-carrier reliability immunity than devices with 1100A GC liner-SiN do. We believed that thicker GC liner-SiN (1100A) induce large stress defects and makes damage to the device's channel lattice structure, thus degrading device characteristics. For pMOSFETs, the effects of high tensile stress GC liner-SiN thicknesses on device performance are not apparent. The major factor of mobility improvement is <100> channel orientation Si substrate. It is necessary to optimum high tensile stress GC liner-SiN technology to enhance pMOSFETs reliability.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"32 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114013694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
3D via etch development for 3D circuit integration in FDSOI FDSOI中3D电路集成的蚀刻开发
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563552
J. Knecht, D. Yost, J. Burns, C.K. Chen, C. Keast, K. Warner
{"title":"3D via etch development for 3D circuit integration in FDSOI","authors":"J. Knecht, D. Yost, J. Burns, C.K. Chen, C. Keast, K. Warner","doi":"10.1109/SOI.2005.1563552","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563552","url":null,"abstract":"This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"22 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Electrical characterization of ultra-thin SOI films: comparison of the pseudo-MOSFET and Hg-FET techniques 超薄SOI薄膜的电学特性:伪mosfet和Hg-FET技术的比较
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563532
F. Allibert, N. Bresson, K. Bellatreche, C. Maunand-Tussot, S. Cristoloveanu
{"title":"Electrical characterization of ultra-thin SOI films: comparison of the pseudo-MOSFET and Hg-FET techniques","authors":"F. Allibert, N. Bresson, K. Bellatreche, C. Maunand-Tussot, S. Cristoloveanu","doi":"10.1109/SOI.2005.1563532","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563532","url":null,"abstract":"As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization of these wafers with simple, process-independent, and fast turnaround methods is very important. In this paper, we present for the first time 3 key aspects: (i) properties of UTF down to 10 nm thickness; (ii) comparison of thinning techniques (sacrificial oxidation vs. SCI); and (iii) comparison of pseudo-MOSFET and Hg-FET methods for UTF.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129784751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of new transistor scaling methods on SOI SRAM cell stability 新型晶体管缩放方法对SOI SRAM电池稳定性的影响
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563592
G. Burbach, T. Feudel, M. Horstmann, D. Greenlaw, R. Seltmann, M. Craig, S. Krishnan, N. Leary, N. Kepler, M. Raab
{"title":"Impact of new transistor scaling methods on SOI SRAM cell stability","authors":"G. Burbach, T. Feudel, M. Horstmann, D. Greenlaw, R. Seltmann, M. Craig, S. Krishnan, N. Leary, N. Kepler, M. Raab","doi":"10.1109/SOI.2005.1563592","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563592","url":null,"abstract":"The size of the embedded SRAM is steadily increasing in high-end microprocessors like Athlon64/spl trade/ and Opteron/spl trade/. So the demand for small cell footprints and improved stability has become more challenging. We describe how AMD has recognized and addressed the competing aspects of technology scaling and improved stability in the 90nm technology.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133312647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and evaluation of basic analog circuits in an emerging MuGFET technology 新兴MuGFET技术中基本模拟电路的设计与评估
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563526
G. Knoblinger, F. Kuttner, A. Marshall, C. Russ, P. Haibach, P. Patruno, T. Schulz, W. Xiong, M. Gostkowski, K. Schruefer, C. Cleavelin
{"title":"Design and evaluation of basic analog circuits in an emerging MuGFET technology","authors":"G. Knoblinger, F. Kuttner, A. Marshall, C. Russ, P. Haibach, P. Patruno, T. Schulz, W. Xiong, M. Gostkowski, K. Schruefer, C. Cleavelin","doi":"10.1109/SOI.2005.1563526","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563526","url":null,"abstract":"Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130516659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
The formation of sub-micro partial SOI materials by SIMOX technology SIMOX技术制备亚微偏SOI材料
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563547
Jiayin Sun, Jing Chen, Meng Chen, Xi Wang
{"title":"The formation of sub-micro partial SOI materials by SIMOX technology","authors":"Jiayin Sun, Jing Chen, Meng Chen, Xi Wang","doi":"10.1109/SOI.2005.1563547","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563547","url":null,"abstract":"In this paper, we try to fabricate sub-micro windows in BOX layer. The pattern thermal oxide layer we used for mask implantation was shown. The typical widths of thermal oxide strips are 150nm and /spl sim/75nm and the space of each strips is 1/spl mu/m. The O/sup +/ ions are implanted through the patterned masking oxide. The XTEM images of the SOI structures are shown. The widths of BOX windows are 236nm (left) and 150 nm (right). It is very interesting that the windows are about 75 nm wider than the corresponding masking strips.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132297507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advanced FinFET technology: TiN metal-gate CMOS and 3T/4T device integration 先进的FinFET技术:TiN金属栅CMOS与3T/4T器件集成
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563594
Y. Liu, K. Endo, M. Masahara, E. Sugimata, T. Matsukawa, K. Ishii, H. Yamauchi, T. Shimizu, K. Sakamoto, S. O'Uchi, T. Sekigawa, E. Suzuki
{"title":"Advanced FinFET technology: TiN metal-gate CMOS and 3T/4T device integration","authors":"Y. Liu, K. Endo, M. Masahara, E. Sugimata, T. Matsukawa, K. Ishii, H. Yamauchi, T. Shimizu, K. Sakamoto, S. O'Uchi, T. Sekigawa, E. Suzuki","doi":"10.1109/SOI.2005.1563594","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563594","url":null,"abstract":"As advanced FinFET technologies, we have developed the co-integration techniques of the TiN gated high-performance 3T- and flexible V/sub th/ 4T-FinFETs. By using the conventional reactive sputtering of TiN, the well symmetrical V/sub th/ N- and P-channel 3T-FinFETs and the high V/sub th/-controllable 4T-FinFETs using the resist etch-back process have been demonstrated. The developed technologies are attractive to materialize the high-performance and power-managed FinFET CMOS circuits.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evaluation of ESD characteristics for 65 nm SOI technology 65纳米SOI工艺的ESD特性评价
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563520
S. Mitra, C. Putnam, R. Gauthier, R. Halbach, C. Seguin, A. Salman
{"title":"Evaluation of ESD characteristics for 65 nm SOI technology","authors":"S. Mitra, C. Putnam, R. Gauthier, R. Halbach, C. Seguin, A. Salman","doi":"10.1109/SOI.2005.1563520","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563520","url":null,"abstract":"With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
0.525/spl mu/m/sup 2/ 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers 0.525/spl mu/m/sup 2/ 6T-SRAM位单元，采用45nm全耗尽SOI CMOS技术，金属栅极，高k介电和300mm晶圆上的高源/漏极
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563595
A. Vandooren, C. Hobbs, O. Faynot, P. Perreau, S. Denorme, C. Fenouillet-Béranger, C. Gallon, C. Morin, A. Zauner, G. lmbert, H. Bernard, P. Garnier, L. Gabette, M. Broekaart, M. Aminpur, S. Barnola, N. Loubet, D. Dutartre, T. Korman, G. Chabanne, F. Martin, Y. Le Tiec, N. Gierczynski, S. Smith, C. Laviron, M. Bidaud, I. Pouilloux, D. Bensahel, T. Skotnicki, H. Mingam, A. Wild
{"title":"0.525/spl mu/m/sup 2/ 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers","authors":"A. Vandooren, C. Hobbs, O. Faynot, P. Perreau, S. Denorme, C. Fenouillet-Béranger, C. Gallon, C. Morin, A. Zauner, G. lmbert, H. Bernard, P. Garnier, L. Gabette, M. Broekaart, M. Aminpur, S. Barnola, N. Loubet, D. Dutartre, T. Korman, G. Chabanne, F. Martin, Y. Le Tiec, N. Gierczynski, S. Smith, C. Laviron, M. Bidaud, I. Pouilloux, D. Bensahel, T. Skotnicki, H. Mingam, A. Wild","doi":"10.1109/SOI.2005.1563595","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563595","url":null,"abstract":"A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525/spl mu/m/sup 2/ with good SNM and low leakage.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122653961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices 基于FinFET和三栅极器件的零电容RAM (Z-RAM)电池的保持特性
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563588
C. Bassin, P. Fazan, W. Xiong, C. Cleavelin, T. Schulz, K. Schruefer, M. Gostkowski, P. Patruno, C. Maleville, M. Nagoga, S. Okhonin
{"title":"Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices","authors":"C. Bassin, P. Fazan, W. Xiong, C. Cleavelin, T. Schulz, K. Schruefer, M. Gostkowski, P. Patruno, C. Maleville, M. Nagoga, S. Okhonin","doi":"10.1109/SOI.2005.1563588","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563588","url":null,"abstract":"In this paper we experimentally study for the first time the retention characteristics of Z-RAM cells based on CMOS FinFET and tri-gate devices. A retention time of few milliseconds is measured at room temperature on 100 nm devices. This FinFET based Z-RAM memory will allow manufacturing of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132001522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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