3D via etch development for 3D circuit integration in FDSOI

J. Knecht, D. Yost, J. Burns, C.K. Chen, C. Keast, K. Warner
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引用次数: 7

Abstract

This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.
FDSOI中3D电路集成的蚀刻开发
本文介绍了三维刻蚀工艺的发展。通过蚀刻的氧化物是在Trikon Technologies低压、高密度、螺旋基簇状工具中开发的。在不同的蚀刻压力和晶圆偏置下进行了响应面实验设计(DOE),考察了它们对蚀刻轮廓和蚀刻速率的影响。各向异性蚀刻对于高包装密度是必不可少的。数据和模型之间非常吻合。需要低压和高偏置来获得垂直剖面。较高的蚀刻压力造成过多的聚合物沉积,导致蚀刻停止。低晶圆偏压不能足够快地去除沉积的聚合物,也会导致蚀刻停止。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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