Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs

Abstract

In this work, for 90nm PD-SOI CMOSFETs on <100> Si substrate, the impacts of high tensile stress GC liner-SiN thicknesses on device performance and hot-carrier induced degradations were investigated. For nMOSFETs, devices with 700A GC liner-SiN possess apparent mobility enhancement and hot-carrier reliability immunity than devices with 1100A GC liner-SiN do. We believed that thicker GC liner-SiN (1100A) induce large stress defects and makes damage to the device's channel lattice structure, thus degrading device characteristics. For pMOSFETs, the effects of high tensile stress GC liner-SiN thicknesses on device performance are not apparent. The major factor of mobility improvement is <100> channel orientation Si substrate. It is necessary to optimum high tensile stress GC liner-SiN technology to enhance pMOSFETs reliability.