0.525/spl mu/m/sup 2/ 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers
A. Vandooren, C. Hobbs, O. Faynot, P. Perreau, S. Denorme, C. Fenouillet-Béranger, C. Gallon, C. Morin, A. Zauner, G. lmbert, H. Bernard, P. Garnier, L. Gabette, M. Broekaart, M. Aminpur, S. Barnola, N. Loubet, D. Dutartre, T. Korman, G. Chabanne, F. Martin, Y. Le Tiec, N. Gierczynski, S. Smith, C. Laviron, M. Bidaud, I. Pouilloux, D. Bensahel, T. Skotnicki, H. Mingam, A. Wild
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引用次数: 2
Abstract
A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525/spl mu/m/sup 2/ with good SNM and low leakage.
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