65纳米SOI工艺的ESD特性评价

S. Mitra, C. Putnam, R. Gauthier, R. Halbach, C. Seguin, A. Salman
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引用次数: 10

摘要

随着规模的不断扩大和对更高性能要求的不断驱动,静电放电正成为先进集成电路可靠性的主要挑战。产品必须设计适当的ESD保护电路,以提供足够的鲁棒性,随着设备能力的极限,由于ESD灵敏度而导致的设备可靠性等因素变得更加重要。本文全面评估了65nm SOI工艺中I/O元件的ESD特性。通过使用这些分立元件的适当设计实现,可以实现行业标准的ESD稳健性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Evaluation of ESD characteristics for 65 nm SOI technology
With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.
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