2005 IEEE International SOI Conference Proceedings最新文献_第6页

Retinal implant electrode arrays with 10V SOI CMOS circuitry 采用10V SOI CMOS电路的视网膜植入电极阵列

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563587

M. Okandan, B. Draper, K. Wessendorf, S. Pearson, R. Young

引用次数: 1

A 1V, Ka Band Prescaler with VTControl in 90nm CMOS SOI 基于90nm CMOS SOI的1V, Ka带VTControl预分频器

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563527

R. Ionita, M. Sanduleanu, E. Stikvoort, A. Vladimirescu

引用次数: 1

Analysis of drain-to-body band-to-band tunneling in double gate MOSFET 双栅极MOSFET漏极体带对带隧穿分析

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563573

H. Ananthan, A. Bansal, K. Roy

引用次数: 10

Planar double gate transistors with asymmetric independent gates 具有非对称独立栅极的平面双栅晶体管

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563562

G. Ilicali, W. Weber, W. Rosner, L. Dreeskornfeld, J. Hartwich, J. Kretz, T. Lutz, J. Mazellier, M. Stadele, M. Specht, J. R. Luyken, E. Landgraf, F. Hofmann, L. Risch, R. Kasmaier, W. Hansch

引用次数: 3

Device design considerations for nanoscale double and triple gate FinFETs 纳米级双栅极和三栅极finfet的器件设计考虑

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563549

A. Kranti, G. A. Armstrong

{"title":"Device design considerations for nanoscale double and triple gate FinFETs","authors":"A. Kranti, G. A. Armstrong","doi":"10.1109/SOI.2005.1563549","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563549","url":null,"abstract":"Based on 3D device simulations, we report performance assessment of TG and DG FinFETs for HP, LOP and LSTP logic technologies for the 65 nm technology node. An investigation of s, d, /spl phi//sub m/ and AR shows that DG devices offer higher I/sub on/ (mA/mm) while achieving acceptable values of I/sub off/ (nAJ//spl mu/m) and thus offer greater design flexibility in selecting device parameters as compared to TG FinFETs to meet ITRS targets for all the three logic technologies. TG and DG FinFETs should be designed with lower aspect ratios (1 /spl sim/ 2), along with lower values of fin height and thickness to achieve ITRS projections. If a target value for spacer and doping gradient is set to (0.5)L and 7 nm/dec for both TG and DG FinFETs then EOT and gate workfunction need to be adjusted to achieve the ITRS targets. TG and DG FinFETs with gate workfunction values in the range of 4.62 - 4.72 eV are more likely to meet ITRS targets for HP and LOP technologies whereas higher workfunctions /spl sim/ 4.82 eV would be more suitable for LSTP applications. A spacer width of (0.25)L with a doping gradient of 7 nm/dec would be more suitable for TG FinFETs for achieving ITRS targets for 65 nm and 45 nm nodes, whereas a spacer width of (0.5)L with the same doping gradient would be more appropriate for DG FinFETs. The present work provides valuable design insights in the performance of TG and DG FinFETs and serves as a tool for optimizing device and technological parameters for 65 nm node and below.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114151132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Subterranean photonics using SIMOX 3-D sculpting for optoelectronic integration in silicon-on-insulator 利用SIMOX三维雕刻技术在硅绝缘体上进行光电集成的地下光子学

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563585

T. Indukuri, P. Koonath, B. Jalali

引用次数: 0

Independent gate skewed logic in double-gate SOI technology 双栅极SOI技术中的独立栅极偏斜逻辑

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563543

T. Cakici, H. Mahmoodi, S. Mukhopadhyay, K. Roy

引用次数: 11

Unusual gate current transient behavior in SOI MOSFETs SOI mosfet中不寻常的栅极电流瞬态行为

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563536

M. Bawedin, S. Cristoloveanu, D. Flandre

引用次数: 3

An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications 温度对射频用SOI衬底CPW和MSL影响的研究

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563537

M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J. Raskin, D. Vanhoenacker-Janvier

{"title":"An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications","authors":"M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J. Raskin, D. Vanhoenacker-Janvier","doi":"10.1109/SOI.2005.1563537","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563537","url":null,"abstract":"Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

V/sub th/ control of t/sub pd/-degradation-free FD SOI MOSFET with extremely thin BOX using variable body-factor scheme V/sub /控制t/sub / pd/-无降解FD SOI MOSFET的极薄盒采用可变体因子方案

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563551

T. Ohtou, K. Yokoyama, T. Nagumo, T. Hiramoto

引用次数: 0