An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications

Abstract

Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.