Device design considerations for nanoscale double and triple gate FinFETs

Abstract

Based on 3D device simulations, we report performance assessment of TG and DG FinFETs for HP, LOP and LSTP logic technologies for the 65 nm technology node. An investigation of s, d, /spl phi//sub m/ and AR shows that DG devices offer higher I/sub on/ (mA/mm) while achieving acceptable values of I/sub off/ (nAJ//spl mu/m) and thus offer greater design flexibility in selecting device parameters as compared to TG FinFETs to meet ITRS targets for all the three logic technologies. TG and DG FinFETs should be designed with lower aspect ratios (1 /spl sim/ 2), along with lower values of fin height and thickness to achieve ITRS projections. If a target value for spacer and doping gradient is set to (0.5)L and 7 nm/dec for both TG and DG FinFETs then EOT and gate workfunction need to be adjusted to achieve the ITRS targets. TG and DG FinFETs with gate workfunction values in the range of 4.62 - 4.72 eV are more likely to meet ITRS targets for HP and LOP technologies whereas higher workfunctions /spl sim/ 4.82 eV would be more suitable for LSTP applications. A spacer width of (0.25)L with a doping gradient of 7 nm/dec would be more suitable for TG FinFETs for achieving ITRS targets for 65 nm and 45 nm nodes, whereas a spacer width of (0.5)L with the same doping gradient would be more appropriate for DG FinFETs. The present work provides valuable design insights in the performance of TG and DG FinFETs and serves as a tool for optimizing device and technological parameters for 65 nm node and below.