{"title":"双栅极SOI技术中的独立栅极偏斜逻辑","authors":"T. Cakici, H. Mahmoodi, S. Mukhopadhyay, K. Roy","doi":"10.1109/SOI.2005.1563543","DOIUrl":null,"url":null,"abstract":"Independent gate control of double gate SOI devices (D. Fried, 2003 and L. Mathew, 2004) can be effectively exploited to improve performance and reduce power in sub-50nm circuits. In this paper, we have proposed a skewed logic style using independent gate operation of double gate SOI devices.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Independent gate skewed logic in double-gate SOI technology\",\"authors\":\"T. Cakici, H. Mahmoodi, S. Mukhopadhyay, K. Roy\",\"doi\":\"10.1109/SOI.2005.1563543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Independent gate control of double gate SOI devices (D. Fried, 2003 and L. Mathew, 2004) can be effectively exploited to improve performance and reduce power in sub-50nm circuits. In this paper, we have proposed a skewed logic style using independent gate operation of double gate SOI devices.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563543\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Independent gate skewed logic in double-gate SOI technology
Independent gate control of double gate SOI devices (D. Fried, 2003 and L. Mathew, 2004) can be effectively exploited to improve performance and reduce power in sub-50nm circuits. In this paper, we have proposed a skewed logic style using independent gate operation of double gate SOI devices.
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