2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第8页

A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors 节能非易失性处理器的双阈值方案及安全增强

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00023

Dongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi, Yongpan Liu

{"title":"A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors","authors":"Dongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi, Yongpan Liu","doi":"10.1109/ISVLSI.2018.00023","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00023","url":null,"abstract":"With the increasing scale and decreasing size of the Internet of Things (IoTs) devices, energy harvesting systems have been proposed to power the systems instead of batteries. Addressing the problem that harvested energy is unstable, nonvolatile processors (NVPs) have been proposed to hold intermediate data and avoid frequent program restarting from the beginning. However, NVPs often suffer frequent backup and recovery operations, wasting a lot of energy and system resources. To further improve the performance of NVPs, this paper proposes a dual-threshold method to maximize execution progress by enabling a system to hibernate to wait for power resumption instead of backing up data directly upon power interruptions. In particular, the appropriate retention and backup thresholds are discussed in details in order to achieve the goal of minimizing power failures and maximizing computation progress. In the meantime, the possible attacks to NVPs with dual-threshold and solutions combating these threats are discussed to guarantee NVP's security. The evaluation results show an average of up to 82.3% reduction on power failures and 1.5x speedup on forward progress by the proposed dual-threshold method compared to the conventional single threshold scheme.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132703565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems 数字VLSI系统中带辅助功率晶体管的基于复制的低压降稳压器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00012

Yang Nan, Chenchang Zhan, Guanhua Wang, Linjun He, Han Li

引用次数: 1

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach 稀疏VLSI布局特征提取:一种字典学习方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00094

Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng

引用次数: 10

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs 基于cnn的图像识别节能混合架构设计

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00015

J. Choi, S. Srinivasa, Yasuki Tanabe, J. Sampson, N. Vijaykrishnan

引用次数: 2

Designing and Benchmarking of Double-Row Height Standard Cells 双排高度标准单元格的设计与基准测试

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00022

Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin

引用次数: 6

Designing Scalable Hybrid Wireless NoC for GPGPUs 基于gpgpu的可扩展混合无线NoC设计

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00132

Hui Zhao, Xianwei Cheng, S. Mohanty, Juan Fang

引用次数: 4

Performance Enhancement of Split Length Compensated Operational Amplifiers 分割长度补偿运算放大器的性能增强

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00116

Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha

引用次数: 0

An Asynchronous Analog to Digital Converter for Surveillance Camera Applications 一种用于监控摄像机的异步模数转换器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00039

K. SiddharthR., R. Sunil, Nithin Y. B. Kumar, M. H. Vasantha, E. Bonizzoni

引用次数: 3

Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures 为许多核心架构实现可靠的高吞吐量片上无线通信

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00113

G. Harsha, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb

{"title":"Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures","authors":"G. Harsha, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb","doi":"10.1109/ISVLSI.2018.00113","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00113","url":null,"abstract":"Wireless Networks-on-Chip (WNoCs) have been shown to overcome the scaling challenges of wired NoCs by augmenting them with low latency, low energy, long range wireless links. However, existing wireless implementations face challenges in terms of reliability while providing high communication performance. Single channel communication, the pre-dominant way of implementing WNoCs, are susceptible to channel effects like dispersion, fading, etc. and also provide limited bandwidth. Multi-channel communication, though provides high throughput, are prone to inter-channel and inter-symbol interference. In order to handle both performance and reliability challenges, we propose wireless network design using Orthogonal Frequency Division Multiplexing (OFDM) modulation. The proposed design enables reliable and channel resilient wireless communication, while providing high throughput, concurrent transmissions in WNoC. OFDM, by dividing wide band channel into several smaller sub-channels, overcomes channel dispersion and ISI effects. In the proposed design, OFDM sub-channels are grouped into multiple contiguous bands and assigned to each transceiver in WNoC. By allowing each transceiver to transmit only over assigned group, we enable simultaneous, high bandwidth communications. Evaluations show that proposed design achieves BER of the order 10^-12. Using the concurrent wireless link design, the runtime is improved by 29% and network energy is reduced by 68% as compared to baseline mesh topology.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128015738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Guiding Template-Induced Design Challenges in DSA-MP Lithography DSA-MP光刻中引导模板诱导的设计挑战

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00097

Shao-Yun Fang, Kuo-Hao Wu

引用次数: 0