A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs

Abstract

Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.