2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

Software Support for Heterogeneous Computing 异构计算的软件支持

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00142

Siqi Wang, Alok Prakash, T. Mitra

引用次数: 3

On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems 嵌入式系统中针对不可信软硬件ip的片上数据安全

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00122

S. Gundabolu, Xiaofang Wang

{"title":"On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems","authors":"S. Gundabolu, Xiaofang Wang","doi":"10.1109/ISVLSI.2018.00122","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00122","url":null,"abstract":"State-of-the-art system-on-chip (SoC) field programmable gate arrays (FPGAs) integrate hard powerful ARM processor cores and the reconfigurable logic fabric on a single chip in addition to many commonly needed high performance and high-bandwidth peripherals. The increasing reliance on untrustworthy third-party IP (3PIP) cores, including both hardware and software in FPGA-based embedded systems has made the latter increasingly vulnerable to security attacks. Detection of trojans in 3PIPs is extremely difficult to current static detection methods since there is no golden reference model for 3PIPs. Moreover, many FPGA-based embedded systems do not have the support of security services typically found in operating systems. In this paper, we present our run-time, low-cost, and low-latency hardware and software based solution for protecting data stored in on-chip memory blocks, which has attracted little research attention. The implemented memory protection design consists of a hierarchical top-down structure and controls memory access from software IPs running on the processor and hardware IPs running in the FPGA, based on a set of rules or access rights configurable at run time. Additionally, virtual addressing and encryption of data for each memory help protect confidentiality of data in case of a failure of the memory protection unit, making it hard for the attacker to gain access to the data stored in the memory. The design is implemented and tested on the Intel (Altera) DE1-SoC board featuring a SoC FPGA that integrates a dual-core ARM processor with reconfigurable logic and hundreds of memory blocks. The experimental results and case studies show that the protection model is successful in eliminating malicious IPs from the system without need for reconfiguration of the FPGA. It prevents unauthorized accesses from untrusted IPs, while arbitrating access from trusted IPs generating legal memory requests, without incurring a serious area or latency penalty.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124923365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Detection of Sequential Trojans in Embedded System Designs Without Scan Chains 无扫描链嵌入式系统设计中序列木马的检测

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00128

Pranav Dharmadhikari, A. Raju, R. Vemuri

引用次数: 5

A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things 面向未来物联网的两层异构可重构应用处理器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00130

Prasanna Kansakar, Arslan Munir

{"title":"A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things","authors":"Prasanna Kansakar, Arslan Munir","doi":"10.1109/ISVLSI.2018.00130","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00130","url":null,"abstract":"The Internet of things (IoT) is leading the world into a future of ubiquitous connectivity. The heterogeneity within the IoT domain necessitates a highly flexible, secure, dependable, and energy-efficient IoT processor architecture. In this paper, we propose a novel processor architecture for IoT that renders energy efficiency, high-performance, flexibility, security, and dependability to meet the diverse application requirements. To address the stringent energy efficiency demands of IoT devices, we propose a two-tiered heterogeneous processor architecture that is composed of a high-performance optimized reconfigurable host processor which controls a number of low-power optimized interface processors. The proposed IoT architecture also incorporates reconfigurability in host processors' computing and communication parameters and co-processor extensions to impart flexibility and additional energy savings. The proposed IoT architecture contains various security co-processor extensions to support various security primitives including encryption and decryption, key generation, integrity verification, and device authentication. Finally, the proposed architecture incorporates reliability and dependability through various hardware-and software-based fault tolerance methods. Experimental results present and compare microarchitecture configurations for host and interface processors obtained through an efficient design space exploration methodology. We have implemented selected security and dependability primitives of our proposed IoT architecture on a Xilinx Spartan-6 field-programmable gate array (FPGA). Results reveal that our proposed IoT architecture can attain a speedup of 47.93x while consuming 2.4x lesser energy for furnishing security and dependability primitives as compared to an optimized ARM implementation of similar security and dependability primitives.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Recent Research and Challenges in Multiple Patterning Layout Decomposition 多模式布局分解研究进展与挑战

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00096

I. Jiang, Hua-Yu Chang

引用次数: 0

Lightweight ASIC Implementation of AEGIS-128 AEGIS-128的轻量级ASIC实现

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00054

Anubhab Baksi, V. Pudi, S. Mandal, A. Chattopadhyay

引用次数: 3

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization 基于数据模式表征的STT-MRAM缓存写能量优化

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00068

Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao

引用次数: 2

Minimalistic Perspective to Public Key Implementations on FPGA FPGA上公钥实现的极简视角

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00076

Debapriya Basu Roy, Debdeep Mukhopadhyay

引用次数: 1

Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled Cavity DMFET全填充和部分填充腔生物传感性能优化

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00059

Ankita Porwal, Chitrakant Sahu

{"title":"Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled Cavity","authors":"Ankita Porwal, Chitrakant Sahu","doi":"10.1109/ISVLSI.2018.00059","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00059","url":null,"abstract":"In this paper, a p-channel Dielectric Modulated Field Effect Transistor (DMFET) used as a biosensor has been investigated for the detection of the neutral as well as charged biomolecules. To analyze the detection ability and sensitivity of the device various metrics such as electric field, surface potential, drain current and transconductance are investigated under different bias conditions. For the detection of biomolecules in the cavity, change in threshold voltage is used as sensing parameter. The device shows a threshold voltage shift of 360 mV for K=5. The device sensitivity is observed at different dielectrics and it is found that drain current sensitivity increases with the increasing value of the dielectric constants. The transconductance of the device increases by a value of 6 × 10^-5 A/V for a biosample with K=5 in the cavity. The fabrication process flow of the device has also been proposed to the minimum involvement of complex processes. Further, performance metrics are analyzed at the partially filled cavity and fully filled cavity to observe the effectiveness of this device in the detection of the neutral and charged biomolecules","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121719859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Investigating Reliability and Security of Integrated Circuits and Systems 研究集成电路和系统的可靠性和安全性

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00029

Qiaoyan Yu, Zhiming Zhang, Jaya Dofe

引用次数: 3