Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization

Traditional memory technologies face severe challenges meeting the ever increasing power and memory bandwidth requirements for high performance computing and big-data analysis. Several emerging memory technologies, as promising candidates to replace SRAM or DRAM, have advanced fast. Among them, STT-MRAM can be used to replace SRAM for on chip cache. However, it suffers from high write energy and latency problems. In the paper, we investigate the data patterns written back from SRAM based L1 cache to STT-MRAM based L2 cache to explore the write energy reduction potential. Depending on the data layout within a cache line, redundant bits can be identified and eliminated from write back operations to save STT-MRAM write energy with only a small area overhead. The simulation results validate the effectiveness and efficiency of our proposed method.