2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第2页

TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems 面向嵌入式系统的部分二值化卷积神经网络

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00034

Yingjian Ling, Kan Zhong, Yunsong Wu, Duo Liu, Jinting Ren, Renping Liu, Moming Duan, Weichen Liu, Liang Liang

引用次数: 8

Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption 基于鲁棒逻辑锁定和加密的DSP核心功能混淆

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00133

A. Sengupta, S. Mohanty

引用次数: 4

Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip 基于片上网络的硬件木马攻击的运行时缓解性能下降

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00139

Manoj Kumar Jyv, Ayass Kant Swain, K. SudeendraKumar, S. Sahoo, K. Mahapatra

{"title":"Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip","authors":"Manoj Kumar Jyv, Ayass Kant Swain, K. SudeendraKumar, S. Sahoo, K. Mahapatra","doi":"10.1109/ISVLSI.2018.00139","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00139","url":null,"abstract":"Globalization of semiconductor design and manufacturing has led to several hardware security issues. The problem of Hardware Trojans (HT) is one such security issue discussed widely in industry and academia. Adversary design engineer can insert the HT to leak confidential data, cause a denial of service attack or any other intention specific to the design. HT in cryptographic modules and processors are widely discussed. HT in Multi-Processor System on Chips (MPSoC) are also catastrophic, as most of the military applications use MPSoCs. Network on Chips (NoC) are standard communication infrastructure in modern day MPSoC. In this paper, we present a novel hardware Trojan which is capable of inducing performance degradation and denial of service attacks in a NoC. The presence of the Hardware Trojan in a NoC can compromise the crucial details of packets communicated through NoC. The proposed Trojan is triggered by a particular complex bit pattern from input messages and tries to mislead the packets away from the destined addresses. A mitigation method based on bit shuffling mechanism inside the router with a key directly extracted from input message is proposed to limit the adverse effects of the Trojan. The performance of a 4x4 NoC is evaluated under uniform traffic with the proposed Trojan and mitigation method. Simulation results show that the proposed mitigation scheme is useful in limiting the malicious effect of hardware Trojan.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

PUF-Based Secure Test Wrapper for SoC Testing 基于puf的SoC测试安全测试封装器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00127

K. SudeendraKumar, S. Seth, S. Sahoo, Abhishek Mahapatra, Ayass Kant Swain, K. Mahapatra

{"title":"PUF-Based Secure Test Wrapper for SoC Testing","authors":"K. SudeendraKumar, S. Seth, S. Sahoo, Abhishek Mahapatra, Ayass Kant Swain, K. Mahapatra","doi":"10.1109/ISVLSI.2018.00127","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00127","url":null,"abstract":"The increased testability and observability due to test structures make chips vulnerable to side channel attacks. The intention of side channel attack are leaking secret keys used in cryptographic cores and getting access to trade related sensitive information stored in chips. Several countermeasures against test based side-channel attacks are available in research literature. One such countermeasure scheme is password based access protection to IEEE 1500 test wrapper, such that only an authentic user with valid password is allowed to access the test structures. IEEE 1500 is a core test standard for enabling the streamlined test integration and test reuse. The trust model of existing schemes assume outsourced assembly and test (OSAT) centre are completely trusted and design house will share secret keys to unlock the IEEE 1500 wrapper during testing. In this paper, we propose a Physical Unclonable Function (PUF) based technique incorporating challenge-response to support comprehensive test security in which there is no need for design house to share secret keys with untrusted OSAT centre to unlock the scan chains. The proposed scheme comes at the cost of reasonable area and performance overhead.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116786359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Robust Timing Attack Countermeasure on Virtual Hardware 虚拟硬件鲁棒定时攻击对策

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00036

Kai Yang, Jungmin Park, M. Tehranipoor, S. Bhunia

{"title":"Robust Timing Attack Countermeasure on Virtual Hardware","authors":"Kai Yang, Jungmin Park, M. Tehranipoor, S. Bhunia","doi":"10.1109/ISVLSI.2018.00036","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00036","url":null,"abstract":"Field programmable gate arrays (FPGAs) are being increasingly used in Internet of Things (IoT) applications, as they usually provide lower power, lower latency and higher performance compared with their processor counterparts. However, security has emerged as a critical concern for FPGA-based systems as they are vulnerable to different form of physical attacks, such as side-channel attacks (SCAs). Existing protection methods, which primarily rely on bitstream encryption, are computationally expensive and more importantly, cannot protect against run-time attacks. Hardware virtualization, where instead of traditional direct mapping to FPGA, an application is mapped upon an application-specific virtual layer, called overlay, has been well-studied in past decades for productivity benefit, while its security implication has not been investigated at all. In this paper, for the first time to our knowledge, we present a novel usage of virtualization that limits damage from timing attacks and improves performance for RSA decryption by employing unique reconfigurable hardware architectures on FPGAs. Specific masking methods are implemented onto this architecture, and extensive security and performance analysis are done that demonstrates significant side-channel attack resistance under performance constraint.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124694789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Achieving Low Power Classification with Classifier Ensemble 用分类器集成实现低功耗分类

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00014

Fanglei Hu, Min Zhang, Hailong Jiao

引用次数: 0

91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications 91dB动态范围9.5nW低通滤波器，用于生物医学应用

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00088

M. Reddy, Sreenivasulu Polineni, Laxminidhi Tonse

引用次数: 6

A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling 基于动态频率缩放的高效电流型PWM DC-DC降压变换器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00090

Ankit Rehani, Sujay Deb, P. Bahubalindruni, Bhavin Odedara, S. Bojja

引用次数: 1

Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults 提高基于pcm的主存寿命，有效恢复卡故障

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00072

Marjan Asadinia, C. Bobda

{"title":"Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults","authors":"Marjan Asadinia, C. Bobda","doi":"10.1109/ISVLSI.2018.00072","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00072","url":null,"abstract":"Among several nonvolatile memory (NVM) candidates, PCM is selected as an attractive replacement to DRAM and comes with both challenges and opportunities. It has beautiful characteristics like non-volatility, better scalability, and lower leakage power. However, limited write endurance is the main burden toward its adoption in practice. It means that after a certain number of writes, some memory cells permanently stuck at either '0' or '1'. To solve this problem and provide strong fault tolerant system, some recovery techniques with minimal storage overhead are required. In this work, we propose a recovery mechanism that relies on static partitioning of a data block into some small number of groups and spreading out faults across the groups uniformly. We then exploit inversion mechanism along with shifting mechanism to continue the use of the failed cell with stuck-at value. So, our proposed method can recover multi bit stuck at faults per partition. Compare to the existing mechanisms, our experimental results for multi-threaded workloads reveal considerable improvement in lifetime and the number of recoverable failures per data block","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127342178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Floorplanning in Graphene Nanoribbon (GNR) Based Circuits 基于石墨烯纳米带(GNR)电路的平面规划

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00061

Subrata Das, D. K. Das

引用次数: 0