Floorplanning in Graphene Nanoribbon (GNR) Based Circuits

Abstract

In this paper, we propose a technique for floorplanning in case of graphene nanoribbon (GNR) based circuits. Graphene nanoribbon based devices and interconnects are now found to be better alternatives over traditional CMOS based devices and interconnects. Logic blocks of GNR can be assumed to be hexagonal in shape. Due to special geometric structure in GNR, the interconnects can be bent only in 0°, 60° and 120° angles. Hence routing grids are aligned to these angles only. The concept of floorplanning in traditional VLSI design is extended first time for GNR based circuits in this paper.