2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第3页

A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors 用于能量收集物联网传感器的375 nA输入关闭电流施密特触发LDO

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00043

K. Ishibashi, Shiho Takahashi

引用次数: 2

Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey CPU, GPU和FPGA性能和功耗的预测建模:调查

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00143

Kenneth O'Neal, P. Brisk

{"title":"Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey","authors":"Kenneth O'Neal, P. Brisk","doi":"10.1109/ISVLSI.2018.00143","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00143","url":null,"abstract":"CPUs and dedicated accelerators (namely GPUs and FPGAs) continue to grow increasingly large and complex to support todays demanding performance and power requirements. Designers are tasked with evaluating the performance and power of similarly increasingly large design spaces during pre-silicon design for CPUs and GPUs to reduce time-to-market and limit manufacturing costs, or to figure out how to best map applications onto FPGAs using high-level synthesis tools. Typically, cycle-accurate simulators are used to evaluate workloads for pre-silicon CPUs and GPUs and to avoid the overhead of synthesis and place-and-route when targeting FPGAs; however, simulators exhibit prohibitively long run times that limit the number of design points and workloads that can be evaluated in a reasonable timeframe. This survey focuses on predictive modeling as an alternative to cycle-accurate simulation, which enables rapid evaluation of workloads and design points. When applied properly, predictive modeling can improve time to market, and can facilitate more comprehensive design space explorations with far less overhead than simulation. The survey focuses on predictive models applied to CPUs, GPUs, and FPGAs, noting that the general approach has been applied to many other computing platforms as well.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130226816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Exploration on Routing Configuration of HNoC with Reasonable Energy Consumption 合理能耗的HNoC路由配置探索

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00140

Juan Fang, Zeqing Chang, Yanjin Cheng, Hui Zhao

引用次数: 4

Hardware Implementation of Reconfigurable Separable Convolution 可重构可分离卷积的硬件实现

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00051

L. Rao, Bin Zhang, Jizhong Zhao

引用次数: 0

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm 使用最近邻算法最大扩展内部可观察性的硅调试

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00019

Ankit Jindal, Binod Kumar, Nitish Jindal, M. Fujita, Virendra Singh

引用次数: 5

MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks MAT:一种减轻对抗性攻击的多强度对抗性训练方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00092

Chang Song, Hsin-Pai Cheng, Huanrui Yang, Sicheng Li, Chunpeng Wu, Qing Wu, Yiran Chen, H. Li

{"title":"MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks","authors":"Chang Song, Hsin-Pai Cheng, Huanrui Yang, Sicheng Li, Chunpeng Wu, Qing Wu, Yiran Chen, H. Li","doi":"10.1109/ISVLSI.2018.00092","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00092","url":null,"abstract":"Some recent work revealed that deep neural networks (DNNs) are vulnerable to so-called adversarial attacks where input examples are intentionally perturbed to fool DNNs. In this work, we revisit the DNN training process that includes adversarial examples into the training dataset so as to improve DNN's resilience to adversarial attacks, namely, adversarial training. Our experiments show that different adversarial strengths, i.e., perturbation levels of adversarial examples, have different working ranges to resist the attacks. Based on the observation, we propose a multi-strength adversarial training method (MAT) that combines the adversarial training examples with different adversarial strengths to defend adversarial attacks. Two training structures—mixed MAT and parallel MAT—are developed to facilitate the tradeoffs between training time and hardware cost. Our results show that MAT can substantially minimize the accuracy degradation of deep learning systems to adversarial attacks on MNIST, CIFAR-10, CIFAR-100, and SVHN. The tradeoffs between training time, robustness, and hardware cost are also well discussed on a FPGA platform.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127716784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

PPAP and iPPAP: PLL-Based Protection Against Physical Attacks PPAP和iPPAP:基于pl的物理攻击防护

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00118

P. Ravi, S. Bhasin, J. Breier, A. Chattopadhyay

{"title":"PPAP and iPPAP: PLL-Based Protection Against Physical Attacks","authors":"P. Ravi, S. Bhasin, J. Breier, A. Chattopadhyay","doi":"10.1109/ISVLSI.2018.00118","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00118","url":null,"abstract":"Digital security practitioners are facing enormous challenge in face of the growing repertoire of physical attacks, e.g., Side Channel Attack (SCA) and Fault Injection Attack (FIA). Countermeasures to such threats are usually very different in nature and come with a significant performance penalty. While the FIA countermeasures rely on fault-detecting sensors or concurrent error detection schemes, SCA countermeasures are based on data masking or dual-rail logic circuits. Recently, a low-overhead FIA countermeasure has been proposed that utilises a ring oscillator circuit with Phase-Locked Loop (PLL). In this paper, we extend that countermeasure to further provide protection against SCA, thereby proposing PLL based Protection Against Physical attacks (PPAP). We demonstrate the PPAP on an FPGA prototype under rigorous SCA and FIA testing. We evaluate SCA resistance using the TVLA metric and observe a 2000x increase in SCA protection (in terms of number of traces) with PPAP. We further improve the security of PPAP using statistical analysis through an improved PPAP design (iPPAP) with an increase in SCA resistance of at least 5000x compared to the unprotected implementation with a minimal area overhead.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127999913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks FPAP:卷积神经网络高效计算的折叠结构

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00098

Yizhi Wang, Jun Lin, Zhongfeng Wang

{"title":"FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks","authors":"Yizhi Wang, Jun Lin, Zhongfeng Wang","doi":"10.1109/ISVLSI.2018.00098","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00098","url":null,"abstract":"Convolutional neural networks (CNNs) have found extensive applications in practice. However, weight/activation's sparsity and different data precision requirements across layers lead to a large amount of redundant computations. In this paper, we propose an efficient architecture for CNNs, named Folded Precision-Adjustable Processor (FPAP), to skip those unnecessary computations with ease. Computations are folded in the following two aspects to achieve efficient computing. On one hand, the dominant multiply-and-add (MAC) operations are performed bit-serially based on a bit-pair encoding algorithm so that the FPAP can adapt to different numerical precisions without using multipliers with long data width. On the other hand, a 1-D convolution is undertaken by a multi-tap transposed finite impulse response (FIR) filter, which is folded into one tap so that computations involving zero activations and weights can be easily skipped. Equipped with the precision-adjustable MAC unit and the folded FIR filter structure, a well-designed array architecture, consisting of many identical processing elements is developed, which is scalable for different throughput requirements and highly flexible for different numerical precisions. Besides, a novel genetic algorithm based kernel reallocation scheme is introduced to mitigate the load imbalance issue. Our synthesis results demonstrate that the proposed FPAP can significantly reduce the logic complexity and the critical path over the corresponding unfolded design, which only delivers slightly higher throughput when processing sparse and compact models. Our experiments also show that FPAP can scale its energy efficiency from 1.01TOP/s/W to 6.26TOP/s/W under 90nm CMOS technology when different data precisions are used.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134006911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Multi-block APUF with 2-Level Voltage Supply 带2级电压电源的多块APUF

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00067

Yunxi Guo, Timothy Dee, A. Tyagi

引用次数: 2

End-to-End Industrial Study of Retiming 端到端重定时工业研究

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00046

Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, M. Choudhury, Victor N. Kravets, A. Sullivan, M. Ciesielski, G. Micheli

{"title":"End-to-End Industrial Study of Retiming","authors":"Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, M. Choudhury, Victor N. Kravets, A. Sullivan, M. Ciesielski, G. Micheli","doi":"10.1109/ISVLSI.2018.00046","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00046","url":null,"abstract":"Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic without changing the functionality. Despite significant efforts spent on sequential optimization since 1980's, there are few works? discussed its performance in an end-to-end design flow. The retiming algorithms were mostly evaluated at the logic level. However, it turns out that the retiming results at logic level could be significantly different than evaluating the physical level. This paper provides the findings of how retiming algorithms perform in an end-to-end industrial design flow, with seven industry designs taken from a recent 14nm microprocessor. Experiments are conducted with several complete industrial design flows. The evaluations are made at the end of the physical design flow. The experimental results show that the performance (design quality) of the retiming algorithms vary on the designs. Based these experimental results, we discover a feature that describes the retiming potentials of sequential designs. This model successfully forecast whether the given industrial designs could be significantly improved by retiming in an end-to-end design flow, regarding timing, area, and power.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9