Multi-block APUF with 2-Level Voltage Supply

Abstract

Physical Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from device manufacturing variations. Arbiter PUFs (APUFs) are a widely used class of PUF detecting process variations by exploiting the propagation delay differences between signals. However, both FPGA and ASIC implementations of APUFs suffer from systematic bias caused by either asymmetric routing or gradient effects in wafer doping. In this work, we introduce an improved APUF ASIC implementation achieving entropy enhancement without increasing area and power consumption significantly. In this design, a selector chain is divided into multiple blocks to avoid accumulation of systematic variation. Different voltage supplies are chosen for selector chain and arbiter circuit to overcome reliability problems produced by short chains. Cadence Monte Carlo sampling on 256-stage APUFs built in IBM 0.13µm technology shows the proposed Multi-Block (MB-) APUFs provide inter-chip uniqueness and reproducibility similar to double APUF (DAPUF); compared to DAPUF with similar uniqueness performance, MBAPUFs decrease area and power consumption by a factor of 2.