Hardware Implementation of Reconfigurable Separable Convolution

Abstract

Convolution operations occupy large amounts of computation resource in convolutional neural networks (CNNs). Separable convolution can greatly reduce computational complexity. Unfortunately, most trained kernels in CNNs are not separable. In this paper, least squares approach is applied to decompose a non-separable 2D kernel into two 1D kernels. A reconfigurable convolutional architecture is proposed to convert a 2D convolution into 1D convolution in convolutional layers. Moreover, a denoising CNN is mapped to the proposed convolution architecture. Experimental results show that the hardware architecture can restore a 1280 720 image in 0.83s, which achieves an 8.4 speed-up over GPU implementation. Verification experiments demonstrate that our approach and hardware architecture can drastically reduce the computational complexity in convolution operations without sacrificing the performance.