2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第4页

An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation 集成MaxFit遗传算法- spice框架的2级运算放大器设计自动化

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00040

V. HarshaM., B. Harish

{"title":"An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation","authors":"V. HarshaM., B. Harish","doi":"10.1109/ISVLSI.2018.00040","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00040","url":null,"abstract":"The Electronic Design Automation (EDA) tools have achieved high degree of maturity and reliability over the years for digital design. The design of analog circuits is a challenge attributed to the existence of multi-dimensional tradeoffs among multiple analog performance metrics like gain, bandwidth, power dissipation, supply voltage, input/output impedances, linearity, voltage swings and noise. The analog design proves to be a significant bottleneck in a System on Chip (SoC) implementation due to lack of automation techniques. To address this issue, the algorithms of the functioning of human brain or soft computing techniques can be gainfully deployed. This work proposes an integrated MaxFit Genetic Algorithm (GA) and GA-SPICE framework to achieve multi-objective optimization of analog design automation. The design of two-stage op-amp is demonstrated in this framework to optimize the objectives of open-loop DC gain, phase margin, unity gain-bandwidth, slew rate, power dissipation and area. The design is performed by proposed MaxFit GA programming of op-amp design equations in MATLAB environment and the design is transmitted seamlessly to LTspice to perform SPICE simulations for design verification. The dynamic fitness evaluation on SPICE generated performance metrics at each iteration of GA programming by transmitting them to MATLAB environment enhances the robustness of analog design significantly.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Publisher's Information 出版商的信息

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/isvlsi.2018.00145

引用次数: 0

Logic Synthesis for In-memory Computing Using Resistive Memories 基于电阻式存储器的内存计算逻辑综合

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00075

S. Shirinzadeh, R. Drechsler

引用次数: 7

A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-negative Matrices 一种快速有效的求非负矩阵近似特征值和特征向量的忆阻器方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00108

Chenghong Wang, Zeinab S. Jalali, Caiwen Ding, Yanzhi Wang, S. Soundarajan

{"title":"A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-negative Matrices","authors":"Chenghong Wang, Zeinab S. Jalali, Caiwen Ding, Yanzhi Wang, S. Soundarajan","doi":"10.1109/ISVLSI.2018.00108","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00108","url":null,"abstract":"Throughout many scientific and engineering fields, including control theory, quantum mechanics, advanced dynamics, and network theory, a great many important applications rely on the spectral decomposition of matrices. Traditional methods such as the power iteration method, Jacobi eigenvalue method, and QR decomposition are commonly used to compute the eigenvalues and eigenvectors of a square and symmetric matrix. However, these methods suffer from certain drawbacks: in particular, the power iteration method can only find the leading eigen-pair (i.e., the largest eigenvalue and its corresponding eigenvector), while the Jacobi and QR decomposition methods face significant performance limitations when facing with large scale matrices. Typically, even producing approximate eigenpairs of a general square matrix requires at least O(N^3) time complexity, where N is the number of rows of the matrix. In this work, we exploit the newly developed memristor technology to propose a low-complexity, scalable memristorbased method for deriving a set of dominant eigenvalues and eigenvectors for real symmetric non-negative matrices. The time complexity for our proposed algorithm is O(N^2/Δ) (where Δ governs the accuracy). We present experimental studies to simulate the memristor-supporting algorithm, with results demonstrating that the average error for our method is within 4%, while its performance is up to 1.78X better than traditional methods.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching 基于部分模式匹配的标准单元光刻弱点识别

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00082

Yongfu Li, I. Tseng, Zhao Chuan Lee, V. Perez, Vikas Tripathi, Y. Ong

引用次数: 2

Parametric Circuit Optimization with Reinforcement Learning 参数电路优化与强化学习

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00045

Changcheng Tang, Zuochang Ye, Yan Wang

引用次数: 3

Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs 优化3D集成电路中锥形微通道散热器的精确模型

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00021

L. Hwang, B. Kwon, Martin D. F. Wong

引用次数: 8

Development of High-Stability, Low-Leakage 6Tr-SRAM with Single Data Line and Single Power Supply Using SOTB Process 采用SOTB工艺开发单数据线单电源、高稳定、低泄漏6tr sram

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00077

S. Miyamoto, Nobuaki Kobayashi

{"title":"Development of High-Stability, Low-Leakage 6Tr-SRAM with Single Data Line and Single Power Supply Using SOTB Process","authors":"S. Miyamoto, Nobuaki Kobayashi","doi":"10.1109/ISVLSI.2018.00077","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00077","url":null,"abstract":"This paper proposes a single data line, double-word line 6Tr-SRAM for use in Internet of Things (IoT) devices using a silicon-on-thin-BOX (SOTB) process to achieve a high reliability and a low power consumption. The layout area was reduced compared to a conventional 6Tr structure by using a uniform data line. The proposed SRAM is able to generate multiple electric potentials without the need for additional power sources by employing a self-controllable voltage level (SVL) circuit, which is a simplified form of a DC/DC converter. Further, it expands the operating margin for writes and reads by decreasing the memory-cell supply voltage and increasing the memory-cell supply ground voltage in writes, and by dropping the word line potential when reading. When the variance of the threshold (Vt) was 0 (TT) and the power supply voltage (VDD) was 1.2 V, the read and write margins expanded by multiples of 2.09 and 1.31 of the conventional 6Tr SRAM, respectively. The standby power caused by a leakage when data is being saved under the same conditions was reduced to 9.17% of that of the conventional SRAM. The area overhead the SVL circuit was 1.383% of that of the conventional form.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127870543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model 用三室药代动力学模型生成医用注射剂安全指南

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00062

Cunxi Yu, Heinz Riener, Francesca Stradolini, G. Micheli

引用次数: 0

Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs 间歇供电非易失性fpga的低开销在线检查点

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00052

Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, C. Xue, J. Hu

{"title":"Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs","authors":"Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, C. Xue, J. Hu","doi":"10.1109/ISVLSI.2018.00052","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00052","url":null,"abstract":"Energy harvesting is an attractive way to power future IoT devices since it can eliminate the need for battery or power cables. However, harvested energy is intrinsically unstable. While FPGAs have been widely adopted in various embedded systems, it is hard to survive unstable power since all the memory components in FPGA are based on volatile SRAMs. The emerging non-volatile memory based FPGAs provide promising potentials to keep configuration data during power outages. However, few works have considered implementing efficient runtime intermediate data checkpoint on non-volatile FPGAs. To realize accumulative computation under intermittent power on FPGA, this paper proposes a low-cost design, FC-FPGAs, which utilizes \"scan-chain like\" flip-flops to track intermediate data. Instead of keeping all on-chip intermediate data, FC-FPGA only targets on necessary data that is labeled by off-line analysis and identified by an on-line tracking circuit. The evaluation shows that compared with state-of-the-art, FC-FPGA can realize accumulative computing and significantly reduce computation time and energy over a wide range of unstable power traces.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133623359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3