Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching

Abstract

At advanced process nodes, lithography weak-points can act as major factors of yield losses in manufactured integrated circuits, especially under aggressive design rules. Thus, it is desirable to consider potential lithography weak-point issues during the phase of designing standard cells in order to improve manufacturability of integrated circuits. In this paper, we propose a partial pattern matching methodology, which is based on the use of a combinatorial K-partitioning technique, to identify all of potential lithography weak-points for standard cells in a given standard cell library. In addition, the proposed methodology adopts a pruning technique to minimize false violations, and uses a prioritization technique to prioritize tasks of modifying and/or redesigning standard cells. Compared with a conventional placement-and-routing based methodology, our experimental results show that the proposed methodology can accurately detect more potential lithography weak-points.