{"title":"基于电阻式存储器的内存计算逻辑综合","authors":"S. Shirinzadeh, R. Drechsler","doi":"10.1109/ISVLSI.2018.00075","DOIUrl":null,"url":null,"abstract":"The increasing urge to bypass the issue of the memory bottleneck in the current computer architectures has attracted high attention to in-memory computing enabled by emerging memory technologies such as Resistive Random Access Memory (RRAM). This paper studies in-memory computing from two perspectives, i.e. customized and instruction-based. The customized approach exploits logic representations to synthesize for in-memory computing. The approach proposes design methodologies and optimization algorithms for each representation with respect to area and latency upon the realizations of their logic primitives. The instruction-based approach proposes an automatic compiler to execute instructions on a logic-in-memory computer architecture and optimizes the programs. Experimental results for both approaches reveal considerable improvements compared to the state-of-the-art.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Logic Synthesis for In-memory Computing Using Resistive Memories\",\"authors\":\"S. Shirinzadeh, R. Drechsler\",\"doi\":\"10.1109/ISVLSI.2018.00075\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increasing urge to bypass the issue of the memory bottleneck in the current computer architectures has attracted high attention to in-memory computing enabled by emerging memory technologies such as Resistive Random Access Memory (RRAM). This paper studies in-memory computing from two perspectives, i.e. customized and instruction-based. The customized approach exploits logic representations to synthesize for in-memory computing. The approach proposes design methodologies and optimization algorithms for each representation with respect to area and latency upon the realizations of their logic primitives. The instruction-based approach proposes an automatic compiler to execute instructions on a logic-in-memory computer architecture and optimizes the programs. Experimental results for both approaches reveal considerable improvements compared to the state-of-the-art.\",\"PeriodicalId\":114330,\"journal\":{\"name\":\"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2018.00075\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2018.00075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Logic Synthesis for In-memory Computing Using Resistive Memories
The increasing urge to bypass the issue of the memory bottleneck in the current computer architectures has attracted high attention to in-memory computing enabled by emerging memory technologies such as Resistive Random Access Memory (RRAM). This paper studies in-memory computing from two perspectives, i.e. customized and instruction-based. The customized approach exploits logic representations to synthesize for in-memory computing. The approach proposes design methodologies and optimization algorithms for each representation with respect to area and latency upon the realizations of their logic primitives. The instruction-based approach proposes an automatic compiler to execute instructions on a logic-in-memory computer architecture and optimizes the programs. Experimental results for both approaches reveal considerable improvements compared to the state-of-the-art.