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2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

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Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention 具有视觉注意的神经形态智能图像传感器的像素并行结构
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00053
Md Jubaer Hossain Pantho, Pankaj Bhowmik, C. Bobda
{"title":"Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention","authors":"Md Jubaer Hossain Pantho, Pankaj Bhowmik, C. Bobda","doi":"10.1109/ISVLSI.2018.00053","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00053","url":null,"abstract":"Power reduction and speedup of computer vision designs remain of high interest as image resolutions continue to increase. Neuromorphic-circuits, emulating the behavior of the nervous system, aspire to achieve this goal. In this paper, we present a pixel-parallel 3D-architecture of a neuromorphic image sensor that uses different sampling frequencies in different regions of an image. We design the model as a bottom-up 3D-architecture composing of several hierarchical computational planes where each plane performs different image processing algorithms in parallel. The on-chip attention module dynamically detects regions with relevant information and produces a feedback path to sample those regions with a higher clock frequency, whereas regions with low spatial and temporal information receive less attention. The results show that by sampling non-relevant regions with a lower frequency, the sensor can reduce redundancy and enable high-performance computing at low power.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses 全片数字辅助LDO调节器与改进的调节和瞬态响应
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00038
Han Li, Chenchang Zhan, Ning Zhang
{"title":"Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses","authors":"Han Li, Chenchang Zhan, Ning Zhang","doi":"10.1109/ISVLSI.2018.00038","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00038","url":null,"abstract":"This paper proposes a fully-on-chip mixed-mode low-dropout (LDO) regulator with regulation and transient response enhanced. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. With the help of the digital regulation part, the supported maximum load current is significantly improved. The proof-of-concept LDO design is fabricated in a standard 0.18-mm CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA 基于FPGA的高灵活轻量级高速真随机数发生器
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00079
Faqiang Mei, Lei Zhang, Chongyan Gu, Yuan Cao, Chenghua Wang, Weiqiang Liu
{"title":"A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA","authors":"Faqiang Mei, Lei Zhang, Chongyan Gu, Yuan Cao, Chenghua Wang, Weiqiang Liu","doi":"10.1109/ISVLSI.2018.00079","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00079","url":null,"abstract":"True random number generator (TRNG), plays an important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit and so on to generate the random numbers. These analog circuit based TRNG structures often consume lots of hardware resources, and are not easy to be integrated in digital systems. In this paper, a low-cost and high-speed TRNG has been proposed by using mixed oscillation generated from XOR gates nested multiple ring oscillators (ROs). Multi-group mixed oscillation XOR operation is applied to obtain high-speed output. The proposed TRNG design is implemented on Xilinx Artix-7 XC7A35T-1FTG256C FPGA. It achieves a high performance with throughput up to 160 Mbps and with a usage of 37 FFs and 25 look up tables (LUTs) in the FPGA. The results show that the proposed TRNG design has successfully passed the testing standards of NIST SP800-22 and AIS31. Compared with previous designs, the proposed TRNG design achieves lower hardware resource consumption and higher speed.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123997681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Exploiting Principle of Moving Target Defense to Secure FPGA Systems 利用运动目标防御原理保护FPGA系统安全
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00078
Zhiming Zhang, Qiaoyan Yu
{"title":"Exploiting Principle of Moving Target Defense to Secure FPGA Systems","authors":"Zhiming Zhang, Qiaoyan Yu","doi":"10.1109/ISVLSI.2018.00078","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00078","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) enter a rapid growth era due to their attractive flexibility and CMOS-compatible fabrication process. However, the increasing popularity and usage of FPGAs also drive more motivated attacks on FPGA systems. In this work, we extensively investigate new potential attacks originated from the untrusted computer-aided design (CAD) suite for FPGAs and further propose a series of countermeasures. For the scenario of using FPGAs to replace obsolete components in legacy systems, we propose a Runtime Pin Grounding (RPG) scheme to ground the unused pins and check the pin status at every clock cycle, and exploit the principle of moving target defense (MTD) to develop a hardware MTD (HMTD) method to thwart hardware Trojan attacks. For general FPGA applications, we extend HMTD to an FPGA-oriented MTD (FOMTD) method, which is composed of three defense lines. FPGA emulation results and hardware cost analyses show that the proposed countermeasures are capable of tackling the attacks from malicious CAD tools with acceptable overheads.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129315479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
More Effective Randomly-Designed Microfluidics 更有效的随机设计微流体
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00125
Weiqing Ji, Tsung-Yi Ho, Hailong Yao
{"title":"More Effective Randomly-Designed Microfluidics","authors":"Weiqing Ji, Tsung-Yi Ho, Hailong Yao","doi":"10.1109/ISVLSI.2018.00125","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00125","url":null,"abstract":"Random design of microfluidics is gaining significant attention by creating functional microfluidic chips. Notable merit of random design is that the error-prone design stage is avoided by a library of random chips, which are simulated beforehand using finite element analysis. This paper proposes a methodology for more effective random chip designs, which further optimizes the random chip library to significantly reduce sample consumption. The random design optimization method can be separately loaded as a stand-alone tool and applied to the original chips from the library. Computational simulation results show that the proposed method greatly reduces sample consumption by more than 20% on average in terms of redundant channels. Moreover, the induced deviations in concentrations are mostly less than 0.002, which are negligible in real biomedical applications.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117242894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM MRAM中加速低位宽深度卷积神经网络
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00103
Zhezhi He, Shaahin Angizi, Deliang Fan
{"title":"Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM","authors":"Zhezhi He, Shaahin Angizi, Deliang Fan","doi":"10.1109/ISVLSI.2018.00103","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00103","url":null,"abstract":"Deep Convolution Neural Network (CNN) has achieved outstanding performance in image recognition over large scale dataset. However, pursuit of higher inference accuracy leads to CNN architecture with deeper layers and denser connections, which inevitably makes its hardware implementation demand more and more memory and computational resources. It can be interpreted as ‘CNN power and memory wall’. Recent research efforts have significantly reduced both model size and computational complexity by using low bit-width weights, activations and gradients, while keeping reasonably good accuracy. In this work, we present different emerging nonvolatile Magnetic Random Access Memory (MRAM) designs that could be leveraged to implement ‘bit-wise in-memory convolution engine’, which could simultaneously store network parameters and compute low bit-width convolution. Such new computing model leverages the ‘in-memory computing’ concept to accelerate CNN inference and reduce convolution energy consumption due to intrinsic logic-in-memory design and reduction of data communication.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
TDC: Tagless DRAM Cache
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00026
S. Saranam, M. Mutyam
{"title":"TDC: Tagless DRAM Cache","authors":"S. Saranam, M. Mutyam","doi":"10.1109/ISVLSI.2018.00026","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00026","url":null,"abstract":"Advancements in 3D-stacking technology lead to the usage of stacked DRAM as a last level cache. DRAM caches present multiple design challenges. DRAM cache tag management overhead is one of them because of large area requirement and high access time for look-up. Numerous techniques have been proposed to handle the challenges involved with the DRAM caches. We consider a design choice wherein the tag array storage is removed completely. In this work, we propose a Tagless DRAM Cache (TDC), that completely removes tag array from the DRAM cache and instead, uses the tag-array of the SRAM last level cache (LLC) along with DRAM cache way indices to locate data in the DRAM cache. Experimental evaluation, considering 4-core configuration, shows that TDC achieves a speedup of 9.97% when compared to baseline. Further, TDC shows greater promise by providing reduction in average power consumption by 11.22% and average SRAM LLC miss penalty by 30.8%.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125907025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data 猜对你的密码:用公开的传感器数据解锁智能手机
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00073
David Berend, Bernhard Jungk, S. Bhasin
{"title":"Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data","authors":"David Berend, Bernhard Jungk, S. Bhasin","doi":"10.1109/ISVLSI.2018.00073","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00073","url":null,"abstract":"Modern day smartphones act as daily companions playing a crucial role in tasks far beyond communication. Equipped with various motion and health sensors, private information is continuously processed, while it can be accessed without asking for special permission. In this paper, we show how the permissionless sensor data can be used to reconstruct one's secret PIN for unlocking the phone or gaining access to one's bank account. Harvesting the power of machine learning algorithms, we present a practical attack able to classify all 10,000 possible PIN combinations. Results show up to 83.7% success within 20 tries. Compared to state of the art reporting 74% success on a reduced space of 50 chosen PINs, we report 99.5% success with a single try in a similar setting.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS 具有MCS-CFCS的失配弹性3.5位MDAC
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00041
Satyajit Mohapatra, H. Gupta, N. Mohapatra
{"title":"Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS","authors":"Satyajit Mohapatra, H. Gupta, N. Mohapatra","doi":"10.1109/ISVLSI.2018.00041","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00041","url":null,"abstract":"Modern data converters architectures like pipeline ADC and Current steering DAC depend on component matching to achieve desired resolution. They consist of large arrays of capacitors/current sources that are highly susceptible to systematic effects arising from process variations and temperature gradients. On top of it, 3D integration of mixed signal ICs adjacent to digital chips makes the arrays are prone to local gradients and hot spots. This makes incorporation of certain error compensation schemes at a layout level a priority. In this work, we have proposed an arraying technique that simultaneously compensates for systematic effects and perform significantly better in the presence of rotated parabolic gradients and localized hotspots. We further propose a modified switching scheme that enables realization of 3.5-bit CFCS decoder circuit with minimum logic gates and delay. The performance of the proposed array integrated with the modified switching scheme is verified on the model of a 16-bit 10Msps pipelined ADC using Matlab. The simulation results show significant improvement of linearity (~6-12 dB) over the existing techniques. The various design challenges and strategies to overcome them are discussed in detail.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130445912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hardware Obfuscation Using Strong PUFs 使用强puf的硬件混淆
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00066
Soroush Khaleghi, Wenjing Rao
{"title":"Hardware Obfuscation Using Strong PUFs","authors":"Soroush Khaleghi, Wenjing Rao","doi":"10.1109/ISVLSI.2018.00066","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00066","url":null,"abstract":"IC piracy is a significant security threat, where malicious manufacturers can produce unauthorized extra chips and/or steal the information of a design through reverse engineering attempts. As a countermeasure, hardware obfuscation schemes usually withhold a part of the design (which thereafter constitutes the \"key\") by replacing it with configurable modules. Enforcing the configurable module to be filled in with the withheld key information enables a post-manufacturing activation of each authenticate chip, albeit with a a need to state the threat of a leaked common key. To ensure that each chip has a unique key, Physically Unclonable Functions (PUFs) have been proposed to be integrated with hardware obfuscation. Such a paradigm is constrained to use weak PUFs, because, to uniquely set the key (the content of the configurable module) for each chip, the designer needs to fully characterize the PUFs for all the chips. In this paper, we argue that a powerful attacker in the position of a manufacturer can fully characterize all the weak PUFs, and use any leaked key to break the obfuscation framework. This paper proposes a strong PUF-based hardware obfuscation scheme to effectively prevent IC piracy even in the case of a leaked key from some activated chip.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124678714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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