Md Jubaer Hossain Pantho, Pankaj Bhowmik, C. Bobda
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引用次数: 8
Abstract
Power reduction and speedup of computer vision designs remain of high interest as image resolutions continue to increase. Neuromorphic-circuits, emulating the behavior of the nervous system, aspire to achieve this goal. In this paper, we present a pixel-parallel 3D-architecture of a neuromorphic image sensor that uses different sampling frequencies in different regions of an image. We design the model as a bottom-up 3D-architecture composing of several hierarchical computational planes where each plane performs different image processing algorithms in parallel. The on-chip attention module dynamically detects regions with relevant information and produces a feedback path to sample those regions with a higher clock frequency, whereas regions with low spatial and temporal information receive less attention. The results show that by sampling non-relevant regions with a lower frequency, the sensor can reduce redundancy and enable high-performance computing at low power.