2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第6页

ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification ARCHVerifyr:一种用于架构验证的嵌入式软件驱动方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00049

T. Grimm, D. Lettnin, M. Hübner

引用次数: 0

Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs 预测mosfet对极端电磁干扰的容限

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00114

Nishchay H. Sule, T. Powell, S. Hemmady, P. Zarkesh-Ha

引用次数: 3

An Optimized Architecture For Decomposed Convolutional Neural Networks 分解卷积神经网络的优化结构

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00100

Fangxuan Sun, Jun Lin, Zhongfeng Wang

引用次数: 0

Area Efficient NMOS Based Positive and Negative Voltage Multiplier 基于面积高效NMOS的正负电压倍增器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00013

V. Rana

引用次数: 0

Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method 神秘:神秘化IP核使用一个永远在线的FSM混淆方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00119

A. Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, M. Fazeli, M. Kinsy

{"title":"Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method","authors":"A. Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, M. Fazeli, M. Kinsy","doi":"10.1109/ISVLSI.2018.00119","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00119","url":null,"abstract":"The separation of manufacturing and design processes in the integrated circuit industry to tackle the ever increasing circuit complexity and time to market issues has brought with it some major security challenges. Chief among them is IP piracy by untrusted parties. Hardware obfuscation which locks the functionality and modifies the structure of an IP core to protect it from malicious modifications or piracy has been proposed as a solution. In this paper, we develop an efficient hardware obfuscation method, called Mystic (Mystifying IP Cores), to protect IP cores from reverse engineering, IP overproduction, and IP piracy. The key idea behind Mystic is to add additional state transitions to the original/functional FSM (Finite State Machine) that are taken only when incorrect keys are applied to the circuit. Using the proposed Mystic obfuscation approach, the underlying functionality of the IP core is locked and normal FSM transitions are only available to authorized chip users. The synthesis results of ITC99 circuit benchmarks for ASIC 45nm technology reveal that the Mystic protection method imposes on average 5.14% area overhead, 5.21% delay overhead, and 8.06% power consumption overheads while it exponentially lowers the probability that an unauthorized user will gain access to or derive the chip functionality.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132560812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform 关于如何在PYNQ平台上高效实现深度学习算法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00112

Luca Stornaiuolo, M. Santambrogio, D. Sciuto

引用次数: 20

Communication-Aware Module Placement for Power Reduction in Large FPGA Designs 在大型FPGA设计中降低功耗的通信感知模块放置

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00047

Kalindu Herath, Alok Prakash, Udaree Kanewala, T. Srikanthan

{"title":"Communication-Aware Module Placement for Power Reduction in Large FPGA Designs","authors":"Kalindu Herath, Alok Prakash, Udaree Kanewala, T. Srikanthan","doi":"10.1109/ISVLSI.2018.00047","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00047","url":null,"abstract":"Modern multi-million logic FPGAs allow hardware designers to map increasingly large designs into FPGAs. However, traditional FPGA CAD flows scale poorly for large designs, often producing low quality solutions in terms of performance and power in such cases. To improve the design productivity, modular design methodology partitions a large design into subsystems, compiles them individually and finally collates the individual solutions to complete the mapping process. Existing work has attempted to partition large designs into smaller subsystems, based on the intra-subsystem communication frequencies, to reduce routing power dissipation. However, inter-subsystem communication has not been considered, especially, during the placement stage. In this paper, we first show the adverse effect of ignoring the inter-subsystem communication during the placement stage. Next, we propose an inter-subsystem communication-aware placement technique using a Simulated Annealing based approach to achieve significant power savings. Experimental results show over 7% reduction in routing power when compared to the existing state-of-the-art partitioning flow that does not consider inter-subsystem communication, while the routing power reduction is over 11% when compared to a commercial CAD tool such as Altera Quartus.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114761559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links 通过混合交换和芯片间无线链路的高带宽片外存储器访问

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00028

G. Harsha, H. Mondal, Sujay Deb

引用次数: 2

Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy 基于侧信道功率分析的指纹识别设计防止IC盗版

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00117

James Shey, Naghmeh Karimi, R. Robucci, C. Patel

{"title":"Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy","authors":"James Shey, Naghmeh Karimi, R. Robucci, C. Patel","doi":"10.1109/ISVLSI.2018.00117","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00117","url":null,"abstract":"Intellectual property (IP) and integrated circuit (IC) piracy are of increasing concern to IP/IC providers because of the globalization of IC design flow and supply chains. Such globalization is driven by the cost associated with the design, fabrication, and testing of integrated circuits and allows avenues for piracy. To protect the designs against IC piracy, we propose a fingerprinting scheme based on side-channel power analysis and machine learning methods. The proposed method distinguishes the ICs which realize a modified netlist, yet same functionality. Our method doesn't imply any hardware overhead. We specifically focus on the ability to detect minimal design variations, as quantified by the number of logic gates changed. Accuracy of the proposed scheme is greater than 96 percent, and typically 99 percent in detecting one or more gate-level netlist changes. Additionally, the effect of temperature has been investigated as part of this work. Results depict 95.4 percent accuracy in detecting the exact number of gate changes when data and classifier use the same temperature, while training with different temperatures results in 33.6 percent accuracy. This shows the effectiveness of building temperature-dependent classifiers from simulations at known operating temperatures.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Comprehensive Electro-Optical Model for Silicon Photonic Switches 硅光子开关的综合电光模型

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00024

Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Peng Yang, Zhehui Wang, Luan H. K. Duong

引用次数: 1