An Optimized Architecture For Decomposed Convolutional Neural Networks

Abstract

Convolutional neural networks (CNNs) have found extensive applications in various tasks. However, the state-of-the-art CNNs are both computation-intensive and memory-intensive, which brings tremendous hardware implementation challenges. Various methods have been proposed to reduce the model size and computation complexity of a CNN. Among them, when hardware implementation is considered, the Canonical Polyadic decomposition (CPD) method is more suitable due to the regularity in the decomposed filters. Moreover, the CPD method can be combined with widely used pruning methods to compress the model in further. In this paper, to the best of our knowledge, an efficient hardware architecture for CPD-CNNs is proposed for the first time based on a carefully designed data flow. In detail, a reconfigurable fast convolution unit is introduced to reduce the number of multiplications while handling some commonly-used convolution core operations. The proposed architecture is coded with RTL and synthesized under the TSMC 90nm CMOS technology. Our design achieves an equivalent throughput of more than 3TOP/s under 650MHz clock frequency.