2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第7页

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2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/isvlsi.2018.00001

引用次数: 0

0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR 动态可重构SDR的0.9 ~ 2.5 GHz子采样接收机结构

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00065

Ajinkya Kale, J. Sturm, V. Pasupureddi

{"title":"0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR","authors":"Ajinkya Kale, J. Sturm, V. Pasupureddi","doi":"10.1109/ISVLSI.2018.00065","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00065","url":null,"abstract":"This work proposes an architecture for dynamically reconfigurable multi-standard radio receiver based on the principle of sub-sampling. The proposed receiver has a unique capability to detect the carrier frequency of the incoming signal, estimate its bandwidth and identify if the carrier is present in one of the target standard bands. In addition, sub-sampling is performed at an early stage in the receiver chain to process the signal in the discrete-time domain and to bring the analog-to-digital converter closer to the antenna as in a universal software defined radio (SDR). This adds to the flexibility and reconfigurability which are generally needed for SDR based RF receivers. Moreover, the proposed radio architecture operates at low clock rates, thanks to sub-sampling, leading to less complex clocking circuitry and low power consumption. The proposed receiver architecture RF front-end is modeled in Verilog-AMS behavioral models and the digital signal processing is implemented in Simulink-Matlab. The complete receiver architecture has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS and WLAN) with the carrier frequency ranging from 0.9 GHz to 2.5 GHz with a maximum signal bandwidth of 22MHz and input dynamic range from -109 to -20 dBm.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123577993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High Performance Ternary Multiplier Using CNTFET 使用CNTFET的高性能三元倍增器

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00057

S. K. Sahoo, Krishna Dhoot, R. Sahoo

引用次数: 5

Interconnect Delay Analysis for RRAM Crossbar Based FPGA 基于FPGA的RRAM横杆互连延迟分析

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00101

M. Hashimoto, Yukio Nakazawa, Ryutaro Doi, Jaehoon Yu

引用次数: 1

Can Soft Errors be Handled Securely? 软错误可以安全处理吗?

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00032

Senwen Kan, Jennifer Dworak

引用次数: 0

Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges 实现可配置缓存嵌入式系统的闭环、在线调谐与控制:进展与挑战

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00136

Islam Badreldin, A. Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani

{"title":"Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges","authors":"Islam Badreldin, A. Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani","doi":"10.1109/ISVLSI.2018.00136","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00136","url":null,"abstract":"The cache subsystem is a major contributor to energy consumption in commercial microprocessors used in embedded systems. To reduce energy, designers can perform design space exploration (DSE) to determine a suitable cache configuration that matches system constraints and goals while minimizing energy consumption. Traditionally, this cache tuning step has been a static process where heuristics or analytical models are used to determine an optimal or near-optimal cache configuration prior to runtime given a known application, application set, or application domain. Even though the configuration may change during runtime for different phases of execution, the specific configuration for each phase remains fixed. This static nature is too restrictive for modern, complex embedded systems that are expected to operate under diverse, unknown operating environments, run unknown applications, and with vastly different user quality of experience (QoE) expectations (e.g., smart phones). Therefore, cache tuning must change from a static optimization process to a dynamic optimization process that adapts online during runtime transparently to the user/system needs. The key challenge is determining the configuration that adheres to QoE expectations while minimizing energy consumption without degrading the user experience during DSE. Despite the wealth of progress that has been made, the realization of a closed-loop, fully adaptive, online-tunable cache subsystem still faces many challenges. In this paper, we review the progress made in the area of static and dynamic cache tuning, discuss the challenges that still exist in this area, and propose a predictionassisted control-theoretic framework to address these challenges.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits 二维量子电路近邻实现的新方法

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00063

Anirban Bhattacharjee, Chandan Bandyopadhyay, R. Wille, R. Drechsler, H. Rahaman

引用次数: 24

SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA 基于SAT编码的过通开关FPGA隐身路径问题验证

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00084

Ryutaro Doi, M. Hashimoto

引用次数: 0

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning 基于压缩感知和机器学习的fpga脑机接口

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00137

R. Shrivastwa, V. Pudi, A. Chattopadhyay

{"title":"An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning","authors":"R. Shrivastwa, V. Pudi, A. Chattopadhyay","doi":"10.1109/ISVLSI.2018.00137","DOIUrl":"https://doi.org/10.1109/ISVLSI.2018.00137","url":null,"abstract":"Electrocorticography (ECoG) is a type of electrophysiological monitoring useful for recording the activity from the cerebral cortex. It has emerged as a promising recording technique in brain-computer interfaces (BCI). Compression of these signals is essential for saving power and bandwidth in the novel application scenarios of Health-based IoT and Body Area Networks. However, this task is particularly challenging since, ECoG signals are not compressible either in time domain or in frequency domain. To that end, Block Sparse Bayesian Learning (BSBL) techniques were suggested for the reconstruction of compressed EEG and ECG signals, which is however, computationally demanding. Furthermore, given the heterogeneity in modern computing systems, careful design partitioning is required to most effectively evaluate the particular resources available on the deployed architecture. In this paper, we propose to utilise a combination of compressive sensing and neural network for the compression and reconstruction of ECoG signals, respectively. For the choice of the neural network, a multi-layer perceptron regressor with a stochastic gradient descent solver is developed. For a sample system, we show that the network has a compression ratio of 50%, and reconstruction accuracy of 89.85% after training with a practical, medium-sized dataset. In general, the results show that the most efficient system implementation is a heterogeneous architecture combining a CPU and a fieldprogrammable gate array (FPGA).","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133816644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges 基于流程的生物芯片的设计自动化和测试:过去的成功和未来的挑战

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2018-07-01 DOI: 10.1109/ISVLSI.2018.00123

Tsung-Yi Ho

引用次数: 4