SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA

Ryutaro Doi, M. Hashimoto
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Abstract

FPGA that introduces via-switches, a kind of nonvolatile resistive RAMs, for crossbar implementation is drawing attention due to higher integration density and performance. However, programming those switches arbitrarily in a crossbar is not trivial since a programming voltage must be given through signal wires that are shared by multiple via-switches. Consequently, depending on the previous programming status, unintentional switch programming may occur due to signal detour, which is called sneak path problem. This paper encodes programming operations in via-switch based crossbar into a satisfiability problem and rigidly verifies the sneak path problem. Verification results show that sneak path problems can be solved by imposing a specific programming constraint.
基于SAT编码的过通开关FPGA隐身路径问题验证
FPGA引入了一种非易失性阻性ram——过通开关,以其更高的集成密度和性能而备受关注。然而,在交叉棒中任意编程这些开关并不是微不足道的,因为编程电压必须通过由多个过通开关共享的信号线给出。因此,根据先前的规划状态,由于信号绕行,可能会出现无意的开关规划,这被称为潜行路径问题。本文将基于过通开关的交叉棒的规划操作编码为可满足性问题,并对潜径问题进行了严格验证。验证结果表明,通过施加特定的规划约束,可以解决潜行路径问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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