Interconnect Delay Analysis for RRAM Crossbar Based FPGA

Abstract

FPGAs with novel RRAM-like nano-switches are under development for filling the gap between ASIC and FPGA. In these FPGAs, we need to analyze delay of signal interconnects that include several nano-switches with additional programming interconnects. This paper proposes simplified equivalent circuits for via-switch FPGAs, which enables analysis acceleration without loss of precision. Experimental results show that the proposed simplification increases the circuit simulation speed by 52x and 49x for single-fanout routes and multiple-fanout routes, respectively, on average while the calculation error is within 1.8% on average. When we further apply moment-based delay analysis called D2M to the simplified circuit, the overall average speed up reaches 2,500x and 600x for single-fanout routes and multiple-fanout routes, respectively.