{"title":"无扫描链嵌入式系统设计中序列木马的检测","authors":"Pranav Dharmadhikari, A. Raju, R. Vemuri","doi":"10.1109/ISVLSI.2018.00128","DOIUrl":null,"url":null,"abstract":"Small, low-cost embedded systems implemented as sequential circuits often do not contain scan chains. Malicious trojan circuits, which themselves may be state machines, inserted into such systems are hard to detect. We present an effective methodology to detect sequential trojan circuits inserted into sequential hardware designs without scan chains. The methodology consists of three steps: We use sequential testability metrics, model checking and signal tracing to progressively separate the trojan gates from legitimate circuit gates. We show experimental results demonstrating the effectiveness of the methodology using several test cases.","PeriodicalId":114330,"journal":{"name":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Detection of Sequential Trojans in Embedded System Designs Without Scan Chains\",\"authors\":\"Pranav Dharmadhikari, A. Raju, R. Vemuri\",\"doi\":\"10.1109/ISVLSI.2018.00128\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Small, low-cost embedded systems implemented as sequential circuits often do not contain scan chains. Malicious trojan circuits, which themselves may be state machines, inserted into such systems are hard to detect. We present an effective methodology to detect sequential trojan circuits inserted into sequential hardware designs without scan chains. The methodology consists of three steps: We use sequential testability metrics, model checking and signal tracing to progressively separate the trojan gates from legitimate circuit gates. We show experimental results demonstrating the effectiveness of the methodology using several test cases.\",\"PeriodicalId\":114330,\"journal\":{\"name\":\"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2018.00128\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2018.00128","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Detection of Sequential Trojans in Embedded System Designs Without Scan Chains
Small, low-cost embedded systems implemented as sequential circuits often do not contain scan chains. Malicious trojan circuits, which themselves may be state machines, inserted into such systems are hard to detect. We present an effective methodology to detect sequential trojan circuits inserted into sequential hardware designs without scan chains. The methodology consists of three steps: We use sequential testability metrics, model checking and signal tracing to progressively separate the trojan gates from legitimate circuit gates. We show experimental results demonstrating the effectiveness of the methodology using several test cases.