Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach

Abstract

Recently, in VLSI design for manufacturability (DFM), capturing and representing the intrinsic characteristics of a layout is of great importance. Especially, there has been revival of interest in applying machine learning techniques into DFM field. Feature extraction of layout patterns is imperative before feeding into learning models so that feature representation directly affects performance of machine learning model. In this paper, a literature review of recent progress on VLSI layout feature extraction is firstly conducted. Then, for the first time, we propose a dictionary learning approach wrapped in an online learning model in applications of VLSI layout such as sub-resolution assist feature (SRAF) generation and hotspot detection. With mapping original features into a sparse and low-dimension space, dictionary learning model is benefit to calibrate a machine learning model. The experimental results show that our method not only improves the accuracy of hotspot detection but also boosts F1 score in machine learning model-based SRAF generation with less time overhead.