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2019 International SoC Design Conference (ISOCC)最新文献

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Latency-Insensitive Controller for Convolutional Neural Network Accelerators 卷积神经网络加速器延迟不敏感控制器
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027661
Youngho Seo, Sanghun Lee, Sunwoo Kim, Jooho Wang, Sungkyung Park, C. Park
{"title":"Latency-Insensitive Controller for Convolutional Neural Network Accelerators","authors":"Youngho Seo, Sanghun Lee, Sunwoo Kim, Jooho Wang, Sungkyung Park, C. Park","doi":"10.1109/ISOCC47750.2019.9027661","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027661","url":null,"abstract":"A novel latency-insensitive controller architecture is proposed for a convolutional neural network (CNN) accelerator. It is shown that the proposed architecture not only guarantees the correct operation, regardless of memory latency, but also maximizes the performance. The implementation results show that the latency-insensitive controller occupies only a negligible fraction of the total area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133144779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Data Randomization for Multi-Variant Execution Environment 多变量执行环境下的数据随机化
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027747
Dongil Hwang, Jangseop Shin, Jeehwan Kim, Y. Paek
{"title":"Data Randomization for Multi-Variant Execution Environment","authors":"Dongil Hwang, Jangseop Shin, Jeehwan Kim, Y. Paek","doi":"10.1109/ISOCC47750.2019.9027747","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027747","url":null,"abstract":"The majority of embedded software is written in C/C++ language, which suffers from an abundance of memory vulnerabilities which open gate to attackers to infiltrate into the computer system. Multi-variant execution environment (MVEE) has been proposed to utilize multi-core embedded processors to provide efficient protection against attackers utilizing memory vulnerabilities. The security provided by MVEE depends on the degree of randomization between the variants. Existing MVEEs typically randomize the data layout between the variants, which can fail to detect some attacks based on relative memory errors. In this paper, we propose to apply data space randomization (DSR) to the variants of MVEE to strengthen the security provided by the MVEE. Experiments show that it adds reasonable performance overheads.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115524675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS 180nm CMOS PAM4变送器的适当补偿电路设计
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027703
Yudai Ichii, R. Noguchi, Toshiyuki Inoue, A. Tsuchiya, K. Kishine
{"title":"Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS","authors":"Yudai Ichii, R. Noguchi, Toshiyuki Inoue, A. Tsuchiya, K. Kishine","doi":"10.1109/ISOCC47750.2019.9027703","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027703","url":null,"abstract":"This paper presents compensation circuit design for four-level pulse amplitude modulation (PAM4) transmitters with feed forward equalizing (FFE) in data transmission systems. The signal amplitude in PAM4 is small, particularly when the supply voltage is low. This leads to signal degradation. To maintain signal quality in PAM4 transmitters, we developed a design that performed within the appropriate combiner parameters. We conducted a post-layout simulation in an 180-nm CMOS process to confirm the advantage of the circuit. The rising and falling times were reduced by 7.4% and 2.4% compared with those of a conventional circuit.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Programmable of a Frequency for Concurrent Driving Signals of Touch Screen Controller 触摸屏控制器并发驱动信号的频率可编程
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027667
Jiun Hong, Hyungwon Kim, UnSang Yu, Hongju Lee
{"title":"Programmable of a Frequency for Concurrent Driving Signals of Touch Screen Controller","authors":"Jiun Hong, Hyungwon Kim, UnSang Yu, Hongju Lee","doi":"10.1109/ISOCC47750.2019.9027667","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027667","url":null,"abstract":"The white paper provides simultaneous output sine wave generators using efficient memory access technology for large touch screen controllers. Sine waves of various frequencies are applied simultaneously to the touch screen controller. In memory, address values other than sine wave values are stored as samples. The range of the sine wave frequency and the interval between each frequency provide greater flexibility than conventional configuration methods by adjusting the address calculation algorithm to obtain sample values stored in memory. It also minimizes the amount of memory required by providing sample values from one memory to each sine wave generator to create all necessary sine waves. The sine wave generator was verified using Vivado, and the DAC built in the MaganChip 130mm CMOS process is defined and verified using Virtuoso and Spectre of Cadence.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129880209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application 用于音频应用的改进前馈结构的101 dB动态范围Delta-Sigma调制器
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027739
Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, G. Ahn
{"title":"A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application","authors":"Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, G. Ahn","doi":"10.1109/ISOCC47750.2019.9027739","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027739","url":null,"abstract":"This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes correlated-double-sampling (CDS) technique to attenuate flicker noise of the op-amp in the first integrator. The prototype analog-to-digital converter (ADC) is fabricated in a 0.18 µm CMOS process with an active die area of 0.119 mm2. It achieves a dynamic range (DR) of 101dB, a peak signal-to-noise ratio (SNR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 91.5 dB in a 24kHz signal bandwidth while consuming 1.55 mW from a 1.8 V power supply.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Uncompensated Robust Rail-to-Rail New Amplifier Structure Compatible with Drivers of LCD Panels 与LCD面板驱动器兼容的无补偿鲁棒轨对轨新型放大器结构
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027714
Imtinan B. Attili, S. Mahmoud
{"title":"Uncompensated Robust Rail-to-Rail New Amplifier Structure Compatible with Drivers of LCD Panels","authors":"Imtinan B. Attili, S. Mahmoud","doi":"10.1109/ISOCC47750.2019.9027714","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027714","url":null,"abstract":"A new rail-to-rail amplifier structure that requires no compensation for the use as a channel buffer in column driver ICs of liquid crystal display (LCD) panels is introduced. The proposed amplifier utilizes current splitting technique applied on a rail-to-rail differential pair. Simulation results for 90 nm CMOS technology on LTSPICE under 1 V supply voltage is provided. Open loop simulations show that the proposed amplifier is capable of achieving high DC gain of 75.5 dB, high transconductance of 350μA/V, high output resistance of 22.2 MΩ with a phase margin of 80° and power consumption of 4.7 μWatt. When configured as a buffer, the amplifier exhibits rail-to-rail operation with low total harmonic distortion (THD) ranging from −66 to −53 dB only corresponding to an input voltage ranging from 0.2 to 1 Vp-p at 10 kHz frequency. For a step input, the output has a fast response with a rise and fall time of 1.56μs and 1.5μs respectively.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116193862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio 用于5G毫米波无线电的65nm CMOS 28GHz直接转换接收器
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/isocc47750.2019.9027756
Soyeon Kim, Byeonghyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin
{"title":"A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio","authors":"Soyeon Kim, Byeonghyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/isocc47750.2019.9027756","DOIUrl":"https://doi.org/10.1109/isocc47750.2019.9027756","url":null,"abstract":"This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF receiver is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. The low-noise amplifier is designed in two-stage, in which the first cascode stage performs the single-to-differential conversion by using a transformer load. The mixer is a gilbert-cell active type. The 50-ohm driving buffer performs the differential-to-single conversion for test interface purpose. An external LO signal is fed to a RC polyphase filter, and splits into differential I/Q LO signals. Designed in 65nm CMOS process, extensive electromagnetic simulations after chip layout are carried out to evaluate the performances. The full receiver dissipates 90 mW from a 1.2-V supply. The Rx full-path gives the gain of +27.4 dB, noise figure of 4.6 dB, 1-dB input compression point of -38 dBm, and the baseband channel bandwidth of 1 GHz. The die size is 2 mm2including RF pads.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Development of a Spectral Feature Extraction using Enhanced MFCC for Respiratory Sound Analysis 基于增强MFCC的频谱特征提取方法在呼吸声分析中的应用
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027640
Wally Enrico M. Ingco, R. Reyes, P. Abu
{"title":"Development of a Spectral Feature Extraction using Enhanced MFCC for Respiratory Sound Analysis","authors":"Wally Enrico M. Ingco, R. Reyes, P. Abu","doi":"10.1109/ISOCC47750.2019.9027640","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027640","url":null,"abstract":"Chronic illnesses such as respiratory diseases are among the most persistent health threats in our society nowadays. Fortunately, the emergence of state-of-the-art technologies like Internet of Things (IoT), Machine Learning, and Artificial Intelligence (AI) are available to make monitoring and pre-diagnosis of human health conditions fast and convenient. Nowadays, health services that are accurate, accessible, and convenient are amongst the in-demand in modern medical applications. In this study, an efficient design for a lung sound classifier is explored that utilizes enhanced-Mel frequency cepstral coefficients (eMFCC). Spectral feature extraction based on MFCC is implemented and optimized using MATLAB. MFCC parameters such as frame duration, frameshift, number of filterbank channels, number of cepstral coefficients, and the frequency range are included in this study. The enhanced MFCC feature vectors were extracted using a histogram and were subjected to different machine learning algorithms such as Support Vector Machine (SVM) and K-Nearest Neighbors (KNN). Results show the evaluation of the enhanced MFCC based on sensitivity, specificity, and overall accuracy is higher than the conventional MFCC.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125509033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
63.2pS at 1.2V dynamic comparator in 65nm CMOS technology 63.2pS, 1.2V动态比较器，65nm CMOS技术
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027693
Jun Yuan, Xiaobin Tang
{"title":"63.2pS at 1.2V dynamic comparator in 65nm CMOS technology","authors":"Jun Yuan, Xiaobin Tang","doi":"10.1109/ISOCC47750.2019.9027693","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027693","url":null,"abstract":"A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127852499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks 面向人工神经网络节能处理的位精度可重构数字内存计算宏
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027679
Hyunjoon Kim, Qian Chen, Taegeun Yoo, T. T. Kim, Bongjin Kim
{"title":"A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks","authors":"Hyunjoon Kim, Qian Chen, Taegeun Yoo, T. T. Kim, Bongjin Kim","doi":"10.1109/ISOCC47750.2019.9027679","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027679","url":null,"abstract":"In this work, we propose an in-memory computing macro with 1-16b digital reconfigurable bit-precision for energy-efficient processing of artificial neural networks. The proposed macro consists of 16K (128x128) bitcells. Each bitcell comprises of three functional blocks including a standard 6T SRAM cell for storing a binary weight, an XNOR gate as a bitwise multiplier, and a full-adder for bitwise addition. The digital bitcell array can be reconfigured into parallel row neurons, each with 128 column-shape multiply-and-accumulate (column-MAC) units placed in a row. A 65nm test-chip is fabricated, and the measured energy-efficiency for 1-to-16bit precision is 117.3-to-2.06TOPS/W.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132298181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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