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2019 International SoC Design Conference (ISOCC)最新文献

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A Novel Hybrid Analog Design Optimizer with Particle Swarm Optimization and modern Deep Neural Networks 基于粒子群优化和现代深度神经网络的新型混合模拟设计优化器
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027647
Ahmed Elsiginy, M. Elmahdy, E. Azab
{"title":"A Novel Hybrid Analog Design Optimizer with Particle Swarm Optimization and modern Deep Neural Networks","authors":"Ahmed Elsiginy, M. Elmahdy, E. Azab","doi":"10.1109/ISOCC47750.2019.9027647","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027647","url":null,"abstract":"This work presents a novel hybrid optimization technique that combines a Particle Swarm Optimization (PSO) engine with a multi-output Deep Neural Network (DNN) to obtain a fast and accurate analog circuit optimizer. A Deep Learning supervised regression model is used to replace the slow simulations required in the standard PSO. A CMOS miller-opamp is used as the design problem. Using the hybrid PSO-DNN technique has combined the speed of the DNN model and the accuracy of the PSO. Moreover, Deep Learning modeling has improved the accuracy compared to the standard machine learning techniques.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132828535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 28GHz Quadrature Up-conversion Transmitter in 65nm CMOS for 5G mmWave Radio 用于5G毫米波无线电的65nm CMOS 28GHz正交上转换发射机
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027748
Byeonghyeon Kim, Soyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin
{"title":"A 28GHz Quadrature Up-conversion Transmitter in 65nm CMOS for 5G mmWave Radio","authors":"Byeonghyeon Kim, Soyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/ISOCC47750.2019.9027748","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027748","url":null,"abstract":"A 28GHz RF transmitter is designed in 65nm CMOS for 5G millimeter-wave radio applications. The transmitter is based on a direct-conversion quadrature up-conversion architecture for achieving small silicon area and low power dissipation. The image suppression is improved by adopting I/Q LO mismatch calibration at the LO driving buffer of mixer. The power amplifier is designed in a differential type with cross-coupled neutralized capacitors for stability and reverse-isolation improvement. Combined schematic and EM simulation results show that the transmitter gives the power gain of 37 dB, OP1dB of +5.8 dBm, and Psat of +11.6 dBm. The total transmitter consumes 111 mW from a 1.2 V supply and occupies 1.78 mm2.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimization of Null Convenction Logic Using Gate Diffusion Input 基于门扩散输入的零约定逻辑优化
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027760
Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
{"title":"Optimization of Null Convenction Logic Using Gate Diffusion Input","authors":"Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC47750.2019.9027760","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027760","url":null,"abstract":"Null convention logic is a commonly used delay insensitive paradigm for designing asynchronous circuits. Traditionally, NCL circuits are implemented using static complementary metal oxide semiconductor (CMOS) technology that tends to have large area overhead. To address this issue, a gate diffusion input (GDI) methodology is introduced for realizing NCL circuits. This GDI is a low-power design approach that uses only two transistors to design complex circuits. By using this design technique, a significant reduction area utilization was observed at the expense of latency overhead. To address this limitation, a novel design approach based on GDI methodology is proposed in this paper. The proposed fast GDI (FGDI) approach uses GDI functions F1 and F2 to reduce latency without affecting performance. To evaluate the performance of the FGDI technique, a one-bit full adder was realized in Cadence virtuoso 45nm technology. Compared to GDI implementation, FGDI approach shows a 76% reduction in the latency.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS Subthreshold Balanced Input-Differential Output Four-Quadrant Multiplier for Teager Energy Operator Based Systems 基于Teager能量算子的CMOS亚阈值平衡输入-差分输出四象限乘法器
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027692
S. I. Khan, S. Mahmoud
{"title":"CMOS Subthreshold Balanced Input-Differential Output Four-Quadrant Multiplier for Teager Energy Operator Based Systems","authors":"S. I. Khan, S. Mahmoud","doi":"10.1109/ISOCC47750.2019.9027692","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027692","url":null,"abstract":"The paper presents a subthreshold four-quadrant multiplier targeted for Teager Energy Operator (TEO) based portable systems. The proposed multiplier functions with balanced input-differential output signals at a 1.2 V supply. The multiplier is simulated using 90nm CMOS process of the BSIM4v4.3 model in LTSpice. The input dynamic range is ±60 mV with maximum non-linear deviation under 4.4% at ±60 mV. Total Harmonic Distortion (THD) is under 0.82% for 20mV amplitudes at 11 Hz, 1 kHz and 10 kHz. The bandwidth of the multiplier is 331.1311 kHz at 5Ω and 10 pF load with a standby power of 4.4361 μW.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low Cost Hand Gesture Control in Complex Environment Using Raspberry Pi 树莓派在复杂环境下的低成本手势控制
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027669
Chana Chansri, J. Srinonchat, E. Lim, K. Man
{"title":"Low Cost Hand Gesture Control in Complex Environment Using Raspberry Pi","authors":"Chana Chansri, J. Srinonchat, E. Lim, K. Man","doi":"10.1109/ISOCC47750.2019.9027669","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027669","url":null,"abstract":"This article focuses on implementation in an embedded system with Raspberry Pi to a standalone machine for controlling electronic devices which wirelessly controlled by a hand gesture in the complex environment background. This system uses the RGB camera in combination with Raspberry Pi, a popular device today due to the inexpensive price and reliable performance. The hand gesture detection in each frame uses the radian fingertip analysis technique, a new technique presented which does not require any data training. This technique provides a good robust for light effect and complex environment. The experiment had been tested with the America Sign Language fingerspelling 12 gestures, the results found that 90.83%.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"54 44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of Cardiac Status Indicator and R-R Interval Adjustment Circuits 心脏状态指示器和R-R间隔调节电路的设计
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027742
Sandhya Surendarraj, Palagani Yellappa, J. Choi
{"title":"Design of Cardiac Status Indicator and R-R Interval Adjustment Circuits","authors":"Sandhya Surendarraj, Palagani Yellappa, J. Choi","doi":"10.1109/ISOCC47750.2019.9027742","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027742","url":null,"abstract":"Despite great advancements in medical field, millions of people suffer from cardiac arrhythmia. The solutions for arrhythmia rely largely on early diagnosis and recognition, and therefore in this paper, we have designed a Cardiac Status Indicator and R-R interval (RRI) adjustment circuit to continuously indicate the status of ECG and generate anti-wave to normalize the abnormal waveform for next-generation cardiac pacemakers. The design accurately detects RRI's and for RRI lesser than 0.6s, an anti-wave is generated to suppress extra heartbeats against irregular heartbeats and on the other hand, for RRI greater than 1s, an anti-wave with extra beats is generated to normalize the heartbeat. The simulation is implemented in 0.18µm CMOS process and the circuits operate in the range of 0.9V to 1.8V.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127918828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Visualization of Neuron Data using Nonlinear Technic 使用非线性技术的神经元数据可视化
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027753
Y. Uwate, Y. Nishio, M. Obien, U. Frey
{"title":"Visualization of Neuron Data using Nonlinear Technic","authors":"Y. Uwate, Y. Nishio, M. Obien, U. Frey","doi":"10.1109/ISOCC47750.2019.9027753","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027753","url":null,"abstract":"In our previous study, we have proposed the method to use nonlinear time-series analysis to apply to neuronal data for visualizing a characteristic of neurons. We set up three types of neuron data which are observed at different days. By applying three nonlinear time-series analysis, we confirmed that the youngest neuron has strong activity and the neuronal behavior settles down as the day goes on. In this study, we investigate the effect of the delay parameter of attractor reconstruction of nonlinear time-series analysis. From observed results, we can see that the appropriate value of delay parameter exists to display the network characteristics.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122292989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs 基于离群值感知的时间复用MAC的cnn高能效算法
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027750
Eunji Kwon, Yesung Kang, Seokhyeong Kang
{"title":"Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs","authors":"Eunji Kwon, Yesung Kang, Seokhyeong Kang","doi":"10.1109/ISOCC47750.2019.9027750","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027750","url":null,"abstract":"Convolutional neural networks (CNNs) are computationally intensive, and deep learning hardware should be implemented energy-efficiently for embedded systems or battery-constrained systems. In this paper, we propose an outlier-aware time-multiplexing MAC. We exploit a CNN feature maps' characteristic of being able to express most of the data in a low bit-width except a few large values, which we call ‘outliers' Our outlier-aware time-multiplexing MAC has improved the energy efficiency by up to 21.1% compared to conventional MACs.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131422177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hybrid Hardware Estimation of the Angle of Arrival for Industrial IoT purposes 用于工业物联网目的的到达角的混合硬件估计
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027688
G. Avitabile, A. Florio, G. Piccinni
{"title":"A Hybrid Hardware Estimation of the Angle of Arrival for Industrial IoT purposes","authors":"G. Avitabile, A. Florio, G. Piccinni","doi":"10.1109/ISOCC47750.2019.9027688","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027688","url":null,"abstract":"In this work we present a very simple yet powerful full hardware architecture for Angle of Arrival estimation based on a comparative approach. This kind of system can be used in the field of Industrial IoT for tracking products or connect wireless sensors. The Angle of Arrival information can be used to perform conformal beamforming. First experimental results are reported to validate its performance.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133338444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GPU Architecture Optimization For Mobile Computing 面向移动计算的GPU架构优化
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027715
A. Aldahlawi, Yang-Bin Kim, Kyung Ki Kim
{"title":"GPU Architecture Optimization For Mobile Computing","authors":"A. Aldahlawi, Yang-Bin Kim, Kyung Ki Kim","doi":"10.1109/ISOCC47750.2019.9027715","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027715","url":null,"abstract":"Graphical Processing Units (GPUs) are always criticized for high power consumption due to its massive performance that it can deliver. While GPUs are getting into the mobile market, more power constraints are established. In this work, we evaluate the power gating techniques for GPU cache arrays. The leakage power in active mode is measured at 2.28 µW whereas is sleep mode leakage power is measured at 0.61 µW (26.7% of active mode leakage) and 0.034 µW at off mode (1.5% of active mode leakage) at 1.0V power supply using 45nm standard CMOS process.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134519480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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