A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks

Abstract

In this work, we propose an in-memory computing macro with 1-16b digital reconfigurable bit-precision for energy-efficient processing of artificial neural networks. The proposed macro consists of 16K (128x128) bitcells. Each bitcell comprises of three functional blocks including a standard 6T SRAM cell for storing a binary weight, an XNOR gate as a bitwise multiplier, and a full-adder for bitwise addition. The digital bitcell array can be reconfigured into parallel row neurons, each with 128 column-shape multiply-and-accumulate (column-MAC) units placed in a row. A 65nm test-chip is fabricated, and the measured energy-efficiency for 1-to-16bit precision is 117.3-to-2.06TOPS/W.