63.2pS, 1.2V动态比较器，65nm CMOS技术

2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI:10.1109/ISOCC47750.2019.9027693

Jun Yuan, Xiaobin Tang

{"title":"63.2pS, 1.2V动态比较器，65nm CMOS技术","authors":"Jun Yuan, Xiaobin Tang","doi":"10.1109/ISOCC47750.2019.9027693","DOIUrl":null,"url":null,"abstract":"A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"63.2pS at 1.2V dynamic comparator in 65nm CMOS technology\",\"authors\":\"Jun Yuan, Xiaobin Tang\",\"doi\":\"10.1109/ISOCC47750.2019.9027693\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply\",\"PeriodicalId\":113802,\"journal\":{\"name\":\"2019 International SoC Design Conference (ISOCC)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC47750.2019.9027693\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9027693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种高速动态比较器。通过降低输入级和锁存级共享节点的电压，提高了比较器的速度。采用65nm CMOS技术设计并仿真了该动态比较器。仿真结果表明，该比较器在1.2V电源下实现了63.2ps的延时

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

63.2pS at 1.2V dynamic comparator in 65nm CMOS technology

A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 International SoC Design Conference (ISOCC)

自引率

0.00%

发文量