Latency-Insensitive Controller for Convolutional Neural Network Accelerators

Abstract

A novel latency-insensitive controller architecture is proposed for a convolutional neural network (CNN) accelerator. It is shown that the proposed architecture not only guarantees the correct operation, regardless of memory latency, but also maximizes the performance. The implementation results show that the latency-insensitive controller occupies only a negligible fraction of the total area.