Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, G. Ahn
{"title":"A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application","authors":"Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, G. Ahn","doi":"10.1109/ISOCC47750.2019.9027739","DOIUrl":null,"url":null,"abstract":"This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes correlated-double-sampling (CDS) technique to attenuate flicker noise of the op-amp in the first integrator. The prototype analog-to-digital converter (ADC) is fabricated in a 0.18 µm CMOS process with an active die area of 0.119 mm2. It achieves a dynamic range (DR) of 101dB, a peak signal-to-noise ratio (SNR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 91.5 dB in a 24kHz signal bandwidth while consuming 1.55 mW from a 1.8 V power supply.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9027739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes correlated-double-sampling (CDS) technique to attenuate flicker noise of the op-amp in the first integrator. The prototype analog-to-digital converter (ADC) is fabricated in a 0.18 µm CMOS process with an active die area of 0.119 mm2. It achieves a dynamic range (DR) of 101dB, a peak signal-to-noise ratio (SNR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 91.5 dB in a 24kHz signal bandwidth while consuming 1.55 mW from a 1.8 V power supply.