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PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems 基于锁相环的SSC嵌入式时钟系统时钟和数据恢复
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027672
Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin
{"title":"PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems","authors":"Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin","doi":"10.1109/ISOCC47750.2019.9027672","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027672","url":null,"abstract":"In the paper, we give analysis and comparison for type-2 and type-3 PLLs to develop the clock and data recovery (CDR) for spread-spectrum clocking (SSC) interfaces, respectively. Through theoretical analysis, we observe that the steady-state phase error of type-2 PLL approaches to a constant while the steady-state phase error approaches zero in type-3 PLL. Since the steady-state phase error results in phase offset for CDR to sample data, type-3 PLL can provide an incentive design for SSC applications. In this work, we apply SSC input of 200-kHz modulation frequency and ±10% modulation rate with a triangular-shape frequency modulation for 3 Gb/s data transmission, and the PLL has bandwidth of 4 MHz and phase margin of 60° for simulation. The simulated steady-state phase offsets for type-2 and type-3 PLL CDRs are 1.28UI and 0.004UI, respectively.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133778625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.2 GHz Bandwidth Baseband Analog Circuit in 65nm CMOS for Millimeter-Wave Radio 一种用于毫米波无线电的65nm CMOS 1.2 GHz带宽基带模拟电路
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027652
Jungah Kim, Shinil Chang, Seungsoo Kim, Hyunchol Shin
{"title":"A 1.2 GHz Bandwidth Baseband Analog Circuit in 65nm CMOS for Millimeter-Wave Radio","authors":"Jungah Kim, Shinil Chang, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/ISOCC47750.2019.9027652","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027652","url":null,"abstract":"This paper presents a wide-bandwidth baseband analog (BBA) amplifier circuit in 65 nm CMOS for 5G mm-wave radio applications. The BBA is composed of an input buffer with dc offset cancellation (DCOC), four-stage variable gain amplifiers (VGAs), and 50-ohm driving output buffers. All blocks are designed in differential to enhance the common mode rejection. The DCOC is based on a body-bias control method for mitigating conflict with the gain control part. Designed in 65nm CMOS, the performances are assessed through post-layout simulations. The BBA consumes 30.2 mW from a 1.2 V supply. The total gain range is 6.2 - 34.5 dB. The bandwidth varies from 1.2 to 2.2 GHz across the total gain tuning range. The entire layout size is 0.053 mm2,","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124463585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Micro Darknet For Inference: ESL reference for inference accelerator design 推理微暗网:推理加速器设计的ESL参考
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/isocc47750.2019.9027644
Min-Zhi Ji, Wei-Chung Tseng, Ting Wu, Bo-Rong Lin, C. Chen
{"title":"Micro Darknet For Inference: ESL reference for inference accelerator design","authors":"Min-Zhi Ji, Wei-Chung Tseng, Ting Wu, Bo-Rong Lin, C. Chen","doi":"10.1109/isocc47750.2019.9027644","DOIUrl":"https://doi.org/10.1109/isocc47750.2019.9027644","url":null,"abstract":"For neural network (NN) models applying to low-end edge devices, the memory management is a very important issue because of the limitation of hardware resources. However, current NN frameworks typically allocate a huge memory space for NN models in the initial stage. To reduce memory requirements, we propose a lite NN inference-only framework, MDFI (Micro Darknet for Inference) based on Darknet. We optimize the MDFI C code by a layer-wise memory management and layer-dependency resolving mechanism. According to the experimental results, the average memory consumption of MDFI has 76% reduction compared to Darknet, and the average execution time of MDFI has 8% reduction also.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128007739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Resistive Switching Behavior of Solution-Processed AlOx, based RRAM with Ni and TiN Top Electrode at Low Annealing Temperatures 低退火温度下Ni和TiN顶电极溶液处理AlOx RRAM的电阻开关行为
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/isocc47750.2019.9027657
Zongjie Shen, Cezhou Zhao, Li Yang, Chun Zhao
{"title":"Resistive Switching Behavior of Solution-Processed AlOx, based RRAM with Ni and TiN Top Electrode at Low Annealing Temperatures","authors":"Zongjie Shen, Cezhou Zhao, Li Yang, Chun Zhao","doi":"10.1109/isocc47750.2019.9027657","DOIUrl":"https://doi.org/10.1109/isocc47750.2019.9027657","url":null,"abstract":"Solution-processed AlOxthin film deposited under different annealing temperatures are used to develop metal/AlOx/Pt RRAM devices, with Ni and TiN as the top electrode (TE) to investigate the influence of metal electrode on device performances. In this work, RRAM devices with various performances exhibit typical bipolar resistive switching (RS) characteristics. The difference of work function between the TE and bottom electrode (BE) metals is considered to play a primary role in operation process. With smaller difference of work function, the devices indicate less power consumption and more stable on/off ratio for SET and RESET operations. The Ni/AlOx/Pt devices demonstrate more stable performance with lower SET and RESET operation voltages (<1.3 V), larger on/off ratio (>103), longer retention time (>104 s) and better endurance(>100 cycle).","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133830016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Innovative I/O Budgeting Methodology for Hierarchical SoC Development 面向分层SoC开发的创新I/O预算方法
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027653
M. R. Meher, Wolfgang Ullmann
{"title":"An Innovative I/O Budgeting Methodology for Hierarchical SoC Development","authors":"M. R. Meher, Wolfgang Ullmann","doi":"10.1109/ISOCC47750.2019.9027653","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027653","url":null,"abstract":"This paper introduces a new input/output (I/O) budgeting methodology enabling delayed exchange of updated hierarchical blocks at System-on-Chip (SoC) level without risking the timing and tapeout schedule. We propose a “freeze_interface” concept to re-define the timing constraints for each I/O path of a hierarchical block in a more precise and fine-grain way so that block and SoC level development can be completely independent. The timing budgeting methodology has been formulated and demonstrated by experimental results.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114079851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Peak Variation Detection Using Variable Length Moving Average Filter for Defects Inspection Systems 基于变长移动平均滤波器的缺陷检测系统峰值变化检测
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027754
Ho-Yun Lee, Yeonjin Kim, Do-Yeon Hwang, Jin-Gyun Chung
{"title":"Peak Variation Detection Using Variable Length Moving Average Filter for Defects Inspection Systems","authors":"Ho-Yun Lee, Yeonjin Kim, Do-Yeon Hwang, Jin-Gyun Chung","doi":"10.1109/ISOCC47750.2019.9027754","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027754","url":null,"abstract":"In defects inspection systems, reflected waves are usually corrupted with undesirable signals such as noise and interferences. Thus, to inspect a material accurately, it is desired to remove undesirable signals from the reflected wave. In this paper, a detection method of peak variation of the received signal is proposed. The proposed method is based on a variable length moving average filter to adjust the slope of the received wave as well as to reduce the effect of noise signals. The proposed algorithm is implemented using an FPGA board and it is demonstrated that the implemented system works quite successfully.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128219009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment 大型超市环境下的高性能行人检测器及其嵌入式系统实现
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027682
Kuan-Hung Chen, Jesse Der-Chian Deng, Y. Hwang
{"title":"A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment","authors":"Kuan-Hung Chen, Jesse Der-Chian Deng, Y. Hwang","doi":"10.1109/ISOCC47750.2019.9027682","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027682","url":null,"abstract":"Enabling autonomous driving in hypermarket environments is a new challenge. The whole scenario is very different from traditional outdoor autonomous driving. To navigate in hypermarket environments, the vehicles need to know where all the surrounded pedestrians are. In addition, the detection model must be small enough to be executed in real-time speed on embedded systems. Therefore, we present a high-performance convolutional neural network for detecting moving indoor pedestrians as well as its implementation on embedded systems in this paper. The proposed CNN model can achieve the same high accuracy as YOLO v3 at the cost of only 27% of the original model size. When implemented on an embedded system, i.e., Jetson Xavier, this work achieves 30 fps @ 360p video format.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132405050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Implementation of Integrating a High Resolution Time-to-Digital Converter with an Embedded Processor System on Low-Cost FPGA 高分辨率时数转换器与嵌入式处理器系统集成在低成本FPGA上的实现
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027738
Wei-Da Chen, You-Chen Zhang, H. Liang
{"title":"Implementation of Integrating a High Resolution Time-to-Digital Converter with an Embedded Processor System on Low-Cost FPGA","authors":"Wei-Da Chen, You-Chen Zhang, H. Liang","doi":"10.1109/ISOCC47750.2019.9027738","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027738","url":null,"abstract":"The study presents the auto-calibration architecture for the RO-based Time-to-Digital Converter equipped with Avalon bus interface (TDC-AVB), which can communicate with an embedded NIOS II processor to predict the output frequencies of ring oscillators precisely. Additionally, the dedicated pattern generator configured by the processor can generate any given signal width to a TDC device in order to compensate for process-voltage-temperature (PVT) variations. The real measured results show that the Differential Non-Linearity (DNL) is between [0.98, -0.8] LSB. For 21.14 ns time interval, the TDC can achieve 4.03 ps resolution on average. The proposed system consumes 2346 adaptive LUTs and 2122 registers for the embedded system, and hardware resources of TDC-AVB are only 499 adaptive LUTs and 252 registers.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse 基于物联网的温控温室水培监测与校正系统的研制
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027722
L. K. Tolentino, E. Fernandez, Romeo L. Jorda, Shayne Nathalie D. Amora, Daniel Kristopher T. Bartolata, Joshua Ricart V. Sarucam, J. C. L. Sobrepeña, Kristine Yvonne P. Sombol
{"title":"Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse","authors":"L. K. Tolentino, E. Fernandez, Romeo L. Jorda, Shayne Nathalie D. Amora, Daniel Kristopher T. Bartolata, Joshua Ricart V. Sarucam, J. C. L. Sobrepeña, Kristine Yvonne P. Sombol","doi":"10.1109/ISOCC47750.2019.9027722","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027722","url":null,"abstract":"This paper presents a monitoring and automatic correction system for an aquaponics set-up in a temperature-controlled greenhouse using an Android device through Internet of Things (IoT). The system involves the acquiring of real time data detected by the light intensity sensor, and air temperature and humidity sensor. It also includes the monitoring of the pH level and temperature of the recirculating water of the system and the canopy area of the plant. If the acquired data is not within the threshold range, the correcting devices, namely grow lights, exhaust and inlet fans, evaporative cooler, aerator, and peristaltic buffer device were automatically triggered by the system to correct and achieve its normal status. The Internet remote access includes the effective wireless transmission and reception of data report between the system and an Android unit with the Android application in real-time.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130841727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick 基于哈希算法的区域高效并行神经网络加速器VLSI实现
2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI: 10.1109/ISOCC47750.2019.9027759
Tae Koan Yoo, J. Park, Jong Tae Kim
{"title":"VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick","authors":"Tae Koan Yoo, J. Park, Jong Tae Kim","doi":"10.1109/ISOCC47750.2019.9027759","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027759","url":null,"abstract":"Recently, neural network accelerator has adopted model compression for embedded devices which have limited constraint such as area and power dissipation. However, area efficiency has not been seriously considered for those performances. Among model compression techniques, hashing trick requires the least weight data. Thus, using hashing trick, this paper proposes neural network accelerator whose performance is comparable to others, but its circuit complexity is reduced for an embedded device. With design exploration, we considered various design models, and determined target design and parallel factors for it. For 32nm cell library, our design operated at 200Mhz could be estimated in 32.06mm2 chip area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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