PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems

Abstract

In the paper, we give analysis and comparison for type-2 and type-3 PLLs to develop the clock and data recovery (CDR) for spread-spectrum clocking (SSC) interfaces, respectively. Through theoretical analysis, we observe that the steady-state phase error of type-2 PLL approaches to a constant while the steady-state phase error approaches zero in type-3 PLL. Since the steady-state phase error results in phase offset for CDR to sample data, type-3 PLL can provide an incentive design for SSC applications. In this work, we apply SSC input of 200-kHz modulation frequency and ±10% modulation rate with a triangular-shape frequency modulation for 3 Gb/s data transmission, and the PLL has bandwidth of 4 MHz and phase margin of 60° for simulation. The simulated steady-state phase offsets for type-2 and type-3 PLL CDRs are 1.28UI and 0.004UI, respectively.