Implementation of Integrating a High Resolution Time-to-Digital Converter with an Embedded Processor System on Low-Cost FPGA

The study presents the auto-calibration architecture for the RO-based Time-to-Digital Converter equipped with Avalon bus interface (TDC-AVB), which can communicate with an embedded NIOS II processor to predict the output frequencies of ring oscillators precisely. Additionally, the dedicated pattern generator configured by the processor can generate any given signal width to a TDC device in order to compensate for process-voltage-temperature (PVT) variations. The real measured results show that the Differential Non-Linearity (DNL) is between [0.98, -0.8] LSB. For 21.14 ns time interval, the TDC can achieve 4.03 ps resolution on average. The proposed system consumes 2346 adaptive LUTs and 2122 registers for the embedded system, and hardware resources of TDC-AVB are only 499 adaptive LUTs and 252 registers.