VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick

Recently, neural network accelerator has adopted model compression for embedded devices which have limited constraint such as area and power dissipation. However, area efficiency has not been seriously considered for those performances. Among model compression techniques, hashing trick requires the least weight data. Thus, using hashing trick, this paper proposes neural network accelerator whose performance is comparable to others, but its circuit complexity is reduced for an embedded device. With design exploration, we considered various design models, and determined target design and parallel factors for it. For 32nm cell library, our design operated at 200Mhz could be estimated in 32.06mm2 chip area.