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2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)最新文献

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Development of ultra-violet sensing devices with zinc-oxide thin-films on oxidized nano-porous-silicon substrates 氧化纳米多孔硅基片上氧化锌薄膜紫外传感器件的研制
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707467
K. Wu, C. Tang, Sheng-Chun Lin
{"title":"Development of ultra-violet sensing devices with zinc-oxide thin-films on oxidized nano-porous-silicon substrates","authors":"K. Wu, C. Tang, Sheng-Chun Lin","doi":"10.1109/NMDC.2013.6707467","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707467","url":null,"abstract":"This paper demonstrated the deposition of zinc oxide (ZnO) thin films on oxidized nano-porous-Si (ONPS) substrates. Ultra-violet (UV) sensing devices based on the developed ZnO films had been fabricated and exhibited high photo-responsivity for 300~400-nm incident UV light. The ZnO-on-ONPS devices got a large photo-to-dark current ratio up to 104 at an incident wavelength of 375 nm, indicating their high potential for development of low-cost UV photodetectors.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127254171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resistive switching in Pt/Ta2O5/TiN structure for nonvolatile memory application 用于非易失性存储器的Pt/Ta2O5/TiN结构的电阻开关
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707472
Jian-Yang Lin, Jyun-hao Chen
{"title":"Resistive switching in Pt/Ta2O5/TiN structure for nonvolatile memory application","authors":"Jian-Yang Lin, Jyun-hao Chen","doi":"10.1109/NMDC.2013.6707472","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707472","url":null,"abstract":"The bipolar resistive switching characteristics of the Ta<sub>2</sub>O<sub>5</sub>-based resistive random access memories with a Pt/Ta<sub>2</sub>O<sub>5</sub>/TiN structure are investigated in this work. The proposed device exhibits a small set voltage of 0.76 V. The resistance ratio of ON/OFF state has a good stability with the compliance current of 1mA and 10mA that is useful for the multi-level data storage application. In addition, good endurance larger than 10<sup>5</sup> cycles under pulse switching operation and retention characteristics up to 10<sup>4</sup> s at room temperature have been achieved in this work.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive device reliability and oxide traps distribution analysis by the low frequency noise in ultra-thin body SOI (UTBSOI) MOSFETs 基于超薄体SOI (UTBSOI) mosfet中低频噪声的器件可靠性和氧化物阱分布分析
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707460
Cheng-li Lin, C. Soh, W. Yeh, Chien-Ting Lin, Chun-Ming Wu, Yao-Hsiang Yang, Wei-Yi Chang, Yen-Lun Huang
{"title":"Comprehensive device reliability and oxide traps distribution analysis by the low frequency noise in ultra-thin body SOI (UTBSOI) MOSFETs","authors":"Cheng-li Lin, C. Soh, W. Yeh, Chien-Ting Lin, Chun-Ming Wu, Yao-Hsiang Yang, Wei-Yi Chang, Yen-Lun Huang","doi":"10.1109/NMDC.2013.6707460","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707460","url":null,"abstract":"This study investigates the device characteristics of the ultra-thin body (UTB) SOI MOSFETs with different channel lengths. The device reliability, body charging effect, and oxide trap distribution are also studied. The P-type device reveals more degradation of the threshold voltage than that of N-type device as decreasing the channel length. For the effect of body charging on ultra-thin Si-body, the N-type device appears more serious body-charging effect than that of the P-type device. Additionally, the N-type body-tied UTB SOI MOSFETs w/ and w/o body grounded shows the bulk oxide trap (NBOT) at the SiO2/Si interface is larger than that at poly-Si-gate/SiO2 interface. Additionally, the N-type device reveals the correlated-carrier number mobility fluctuation. For P-type device, the similar carrier-fluctuation appears in the HCI test, but the BTI stress enhances the phenomenon of the carrier-number fluctuation.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123171828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel ultra high voltage sidewall implant super junction MOSFET using arsenic implantation under trench bottom 一种利用沟底下砷注入的超高压侧壁植入超级结MOSFET
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707462
Rahul Kumar, E. Hapsari, G. Sheu, Shao-Ming Yang, K. Anil
{"title":"A novel ultra high voltage sidewall implant super junction MOSFET using arsenic implantation under trench bottom","authors":"Rahul Kumar, E. Hapsari, G. Sheu, Shao-Ming Yang, K. Anil","doi":"10.1109/NMDC.2013.6707462","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707462","url":null,"abstract":"In this paper a novel super junction device with vertical deep trench is proposed which have arsenic implant at the bottom of the trench. The device is a conventional vertical N-channel DMOS with a deep trench adjacent to the gate. The trench forms vertical sidewall into which boron is implanted and diffused to form a P-type doping pillar which is charge balanced to the N-type epitaxial drift region. Boron implantation causes back scattering of ions which is finally collected at the bottom of the trench which contributes to early breakdown of the device. This paper present new technology of sidewall implant super junction using arsenic implantation to compensate for high concentration of bottom at the trench bottom developed by Sentaurus Process and Device technology-computer-aided-design (TCAD) simulators.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of trench depth and trench angle in a high voltage polyflanked-Super junction MOSFET 高压多翼超级结MOSFET中沟槽深度和沟槽角的影响
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707458
Kumar M. P. Vijay, G. Shreyas, K. Nidhi, Neelam Agarwal, Ankit Kumar, G. Sheu, Shao-Ming Yang, Aryadeep Mrinal
{"title":"Effect of trench depth and trench angle in a high voltage polyflanked-Super junction MOSFET","authors":"Kumar M. P. Vijay, G. Shreyas, K. Nidhi, Neelam Agarwal, Ankit Kumar, G. Sheu, Shao-Ming Yang, Aryadeep Mrinal","doi":"10.1109/NMDC.2013.6707458","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707458","url":null,"abstract":"A novel super-junction (SJ) MOSFET based on charge compensation outperforms its conventional counterpart. Several fabrication technologies such as COOLMOS, STM, Multiepitaxy, Sidewall doping technique have been implemented earlier to realize SJ devices. However, its production is limited due to various shortcomings namely, costly fabrication process and inter-diffusion problems. To address both issues and to obtain better performance and process technology for super-junction MOSFET devices, a novel Polyflanked Super-junction (PF-SJ) structure is proposed as an alternative process technology to realize SJ MOSFET. TCAD simulation of the poly-filled trench SJ was done successfully and is reported to break the conventional MOSFET silicon limit for power MOSFET. This structure yields a simple way to realize the SJ performance in a typical production process. Both of its on-state and off-state characteristics are studied taking into account several possibilities of fabrication imperfections, viz., variation in trench etch angle, n and p column concentration for varied trench depths. The results establish the superior performance of PF-SJ compared to the conventional high voltage MOS structure.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129936976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology 工艺集成同类最佳规格电阻20V至60V 0.18µm双极CMOS DMOS技术
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707471
E. Hapsari, Rahul Kumar, G. Sheu, Shao-Ming Yang, T. Anil
{"title":"Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology","authors":"E. Hapsari, Rahul Kumar, G. Sheu, Shao-Ming Yang, T. Anil","doi":"10.1109/NMDC.2013.6707471","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707471","url":null,"abstract":"The evolution of Bipolar CMOS DMOS (BCD) technology leads in the improvement of design technology to produce better device performance with fabrication cost effectiveness as concerned. In this paper, 0.18μm BCD technology with linear p-top layer N-channel LDMOS structure from 20V to 60V is presented with best in class Ron for both N-channel and P-channel LDMOS compared to recent BCD technology works. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116018341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast response gas sensor based on fluorine plasma modified single wall carbon nanotubes 基于氟等离子体修饰单壁碳纳米管的快速响应气体传感器
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707452
Chun-Kuo Liu, H. Shih
{"title":"A fast response gas sensor based on fluorine plasma modified single wall carbon nanotubes","authors":"Chun-Kuo Liu, H. Shih","doi":"10.1109/NMDC.2013.6707452","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707452","url":null,"abstract":"Single wall carbon nanotubes (SWCNTs) were synthesized from chemical vapor deposition (CVD) by decomposition of ethanol over a Fe+Co/MgO heterogeneous catalyst. The SWCNTs were treated by fluorine plasma from microwave plasma enhanced chemical vapor deposition (MPECVD) for surface modification, and developed as novel gas sensor materials. In gas-sensing tests, the SWCNT-based gas sensors treated by fluorine plasma have shown a p-type response with resistance enhancement upon exposure to 50-500 ppm ethanol at room temperature. Fluorine plasma modification can enhance the sensor response (100 ppm) from 1.15 to 1.28 on process duration of 60 s due to the apparent elimination of amorphous carbon, as demonstrated by Raman results. The sensitivity (100 ppm) increases two more times (from 0.0009 to 0.0019) and the linear range of measurement can also extend. In addition, the response and recovery time (100 ppm) can decrease apparently from 195 to 69 s and 374 to 202 s due to the existence of numerous fluorine-included functional groups, as demonstrated by the results of x-ray photoelectron spectroscopy and Auger electron spectroscopy. Therefore, the fluorinated SWCNTs can elevate the sensitivity and reactivity for room temperature ethanol sensing.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116592842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of MoSi2 nanocrystals in nonvolatile memory devices MoSi2纳米晶对非易失性存储器件的影响
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707469
Jian-Yang Lin, Sheng-Chi Chen
{"title":"Effects of MoSi2 nanocrystals in nonvolatile memory devices","authors":"Jian-Yang Lin, Sheng-Chi Chen","doi":"10.1109/NMDC.2013.6707469","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707469","url":null,"abstract":"This work has demonstrated the electron charging and discharging effects of MoSi<sub>2</sub> nanocrystals embedded in the a-Si layer of a nonvolatile memory (NVM) structure. The MoSi<sub>2</sub> nanocrystals were formed by the thermal annealing of the Mo-Si layer. A very thin silicon dioxide layer of 5 nm was deposited as the tunnel dielectric and a significant capacitance-voltage hysteresis of voltage shift was observed by using another SiO<sub>2</sub> layer as the control oxide. The memory window of the SiO<sub>2</sub>/Mo-Si/SiO<sub>2</sub> structure with MoSi<sub>2</sub> nanocrystals is sufficiently high even under low-voltage programming.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A micro plasma reactor chip: Using interface in micro-/nano-channels towards materials processing 一种微等离子体反应器芯片:利用微/纳米通道界面进行材料处理
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707465
M. Hashimoto, R. Sato, S. Kumagai, M. Sasaki
{"title":"A micro plasma reactor chip: Using interface in micro-/nano-channels towards materials processing","authors":"M. Hashimoto, R. Sato, S. Kumagai, M. Sasaki","doi":"10.1109/NMDC.2013.6707465","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707465","url":null,"abstract":"A micro plasma reactor chip was fabricated towards materials processing and synthesis. Within the chip, plasma discharge gas and reactive gas were supplied through microchannels. Due to the narrow size of the channel, Reynolds number was calculated to be small. Laminar flows were generated, which resulted in stable interface formation at a flow junction. In the interface area, the excited species in the plasma discharge decomposed the reactive gas molecules in another flow, thereby generating sheet of reactive atomic/molecular species.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology 基于0.18um BCD工艺技术，设计了一种低阻、高压(<100V)的新型三维NLDMOS
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI: 10.1109/NMDC.2013.6707459
Ankit Kumar, E. Hapsari, Vasantha Kumar, Aryadeep Mrinal, G. Sheu, Shao-Ming Yang, V. Ningaraju
{"title":"Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology","authors":"Ankit Kumar, E. Hapsari, Vasantha Kumar, Aryadeep Mrinal, G. Sheu, Shao-Ming Yang, V. Ningaraju","doi":"10.1109/NMDC.2013.6707459","DOIUrl":"https://doi.org/10.1109/NMDC.2013.6707459","url":null,"abstract":"In this work, a single RESURF P-top layer with STI-sided N-LDMOS device is developed to realize a breakdown voltage of 20V-60V with lowest on-resistance and good charge balance which is demonstrated by using three-dimensional Sentaurus process and device simulators. By tuning not only the doping concentration in substrate, N-drift and P-top layer regions, but also the width ratio of N-drift region divided by STI one (WN-drift/WSTI), a low specific on-resistance while maintaining a high breakdown voltage can be achieved successfully in this work.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133066962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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