工艺集成同类最佳规格电阻20V至60V 0.18µm双极CMOS DMOS技术

2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) Pub Date : 2013-10-01 DOI:10.1109/NMDC.2013.6707471

E. Hapsari, Rahul Kumar, G. Sheu, Shao-Ming Yang, T. Anil

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引用次数: 0

摘要

双极CMOS DMOS (BCD)技术的发展导致了设计技术的改进，以产生更好的器件性能和制造成本效益。本文提出了一种具有线性p-顶层n -沟道LDMOS结构的0.18μm BCD技术，与现有的BCD技术相比，该技术在20V至60V范围内具有最佳的n -沟道LDMOS性能。通过调整发射极宽度和基极硼掺杂浓度对20V BJT的电流增益进行了优化，在击穿电压没有明显变化的情况下，电流增益提高了10倍以上。

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Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology

The evolution of Bipolar CMOS DMOS (BCD) technology leads in the improvement of design technology to produce better device performance with fabrication cost effectiveness as concerned. In this paper, 0.18μm BCD technology with linear p-top layer N-channel LDMOS structure from 20V to 60V is presented with best in class Ron for both N-channel and P-channel LDMOS compared to recent BCD technology works. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.

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2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)

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