Ankit Kumar, E. Hapsari, Vasantha Kumar, Aryadeep Mrinal, G. Sheu, Shao-Ming Yang, V. Ningaraju
{"title":"基于0.18um BCD工艺技术，设计了一种低阻、高压(<100V)的新型三维NLDMOS","authors":"Ankit Kumar, E. Hapsari, Vasantha Kumar, Aryadeep Mrinal, G. Sheu, Shao-Ming Yang, V. Ningaraju","doi":"10.1109/NMDC.2013.6707459","DOIUrl":null,"url":null,"abstract":"In this work, a single RESURF P-top layer with STI-sided N-LDMOS device is developed to realize a breakdown voltage of 20V-60V with lowest on-resistance and good charge balance which is demonstrated by using three-dimensional Sentaurus process and device simulators. By tuning not only the doping concentration in substrate, N-drift and P-top layer regions, but also the width ratio of N-drift region divided by STI one (WN-drift/WSTI), a low specific on-resistance while maintaining a high breakdown voltage can be achieved successfully in this work.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology\",\"authors\":\"Ankit Kumar, E. Hapsari, Vasantha Kumar, Aryadeep Mrinal, G. Sheu, Shao-Ming Yang, V. Ningaraju\",\"doi\":\"10.1109/NMDC.2013.6707459\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a single RESURF P-top layer with STI-sided N-LDMOS device is developed to realize a breakdown voltage of 20V-60V with lowest on-resistance and good charge balance which is demonstrated by using three-dimensional Sentaurus process and device simulators. By tuning not only the doping concentration in substrate, N-drift and P-top layer regions, but also the width ratio of N-drift region divided by STI one (WN-drift/WSTI), a low specific on-resistance while maintaining a high breakdown voltage can be achieved successfully in this work.\",\"PeriodicalId\":112068,\"journal\":{\"name\":\"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)\",\"volume\":\"235 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NMDC.2013.6707459\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NMDC.2013.6707459","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology
In this work, a single RESURF P-top layer with STI-sided N-LDMOS device is developed to realize a breakdown voltage of 20V-60V with lowest on-resistance and good charge balance which is demonstrated by using three-dimensional Sentaurus process and device simulators. By tuning not only the doping concentration in substrate, N-drift and P-top layer regions, but also the width ratio of N-drift region divided by STI one (WN-drift/WSTI), a low specific on-resistance while maintaining a high breakdown voltage can be achieved successfully in this work.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
