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Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)最新文献

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Super-hot-runs management system 超热运行管理系统
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993688
L. Lee, K. Hsieh, M. Lin, R. Luoh, A. Ling, S. Huang
{"title":"Super-hot-runs management system","authors":"L. Lee, K. Hsieh, M. Lin, R. Luoh, A. Ling, S. Huang","doi":"10.1109/ISSM.2000.993688","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993688","url":null,"abstract":"Our project's purpose is to reduce the cycle time of \"push lots\". Some lots must be pushed at a faster speed than normal lots. We refer to these lots as super-hot-runs. For example: If the customer's special requirements includes, pilot lot or FAB potential-lot, our project's purpose is to reduce the cycle times of \"push lots\" (Super-hot-runs, pilot, hot-lots) to ensure maximum customer satisfaction. According to our historical data, the cycle times of push lots were 1.0 days/layer before we started this project. We made a project goal : by reducing the C/T from 1.0 days/layer to 0.8 days/layer. We set the goal by analyzing the percentage of run, queue, hold. Then tuned a reasonable queue time SPEC to meet C/T target. Hold time reduction is also being dealt with in this project.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127041841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Real-time equipment health evaluation and dynamic preventive maintenance 实时设备健康评估和动态预防性维护
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993691
A. Chen, R. Guo, G. Wu
{"title":"Real-time equipment health evaluation and dynamic preventive maintenance","authors":"A. Chen, R. Guo, G. Wu","doi":"10.1109/ISSM.2000.993691","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993691","url":null,"abstract":"With the great advancement of sensor and information technology, the semiconductor equipment data is now available to process engineers in real time. However the volume of data collected and quickly accumulated is often so large that the data is rarely analyzed and put to use effectively. In this paper, we propose an integrated approach that utilizes multivariate statistical techniques to combine various equipment data items into a single equipment health index. We then use this index to determine appropriate time points for equipment preventive maintenance (PM).","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127883561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Module optimization modeling with discrete event simulation 离散事件仿真模块优化建模
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993684
R. Bachrach, M. Pool, R. Sunkara, B. Pang
{"title":"Module optimization modeling with discrete event simulation","authors":"R. Bachrach, M. Pool, R. Sunkara, B. Pang","doi":"10.1109/ISSM.2000.993684","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993684","url":null,"abstract":"Module optimization modeling with discrete event simulation is described. The models allow the organization of tools and chambers and visualization of the modules in different configurations as well as the analysis of the expected performance relative to parameters. Representative results for a Dep/Etch/Dep module are presented.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low cost and short lead time AMHS design using interbay/intrabay diverging and converging IMP method for 300 mm fab 300mm晶圆厂采用间隔/间隔发散和收敛IMP方法进行低成本和短交货期的AMHS设计
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993614
R. Kurosaki, T. Shimura, H. Komada, T. Kojima, Y. Watanabe
{"title":"Low cost and short lead time AMHS design using interbay/intrabay diverging and converging IMP method for 300 mm fab","authors":"R. Kurosaki, T. Shimura, H. Komada, T. Kojima, Y. Watanabe","doi":"10.1109/ISSM.2000.993614","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993614","url":null,"abstract":"A 300 mm generation automatic transport system, transport system with the \"interbay and intrabay diverging and converging method\" (the diverging/converging method) using OHT has been proposed. Its practical utilization however has been retarded because this method requires a large system scale, and therefore requires very sophisticated control. We have formulated a plan of combining two or more diverging/converging systems and connecting them by stockers. The result of simulation has indicated that a shorter lead time and low-cost transport system could be constructed with this method.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128818590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Novel coating apparatus using nozzle-scan technique 采用喷嘴扫描技术的新型涂层装置
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993696
T. Kitano
{"title":"Novel coating apparatus using nozzle-scan technique","authors":"T. Kitano","doi":"10.1109/ISSM.2000.993696","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993696","url":null,"abstract":"Scan coating is a technique that coats material like painting on the wafer. In this paper, we introduce the scan coating technology that enables to replace the spin coating. To make film thicker with a smaller volume of dispensed solution, the nozzle diameter was decreased to 20-100 /spl mu/m. The dispensing time at the outside of wafer was also greatly reduced. Here waste rate is defined as a ratio of wasted materials to all dispensed material, the waste rate is 10% when an acceleration of the nozzle is 200 m/sec/sup 2/. This is nine times less than that for conventional spin coating; its waste rate is 90%. The scan coating has an advantage of pattern coverage on a topological wafer since the dispensed material is not stretched on the wafer by a centrifugal force. Because material's evaporation is quite low during the scan coating, the temperature change of the wafer is very small. This results in better film thickness uniformity. The scan coating may solve current problems of the spin coating technique such as larger material consumption, coating uniformity on the topological wafers, and wafer temperature control.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133906180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A method of RIE treatment to enhance the contour of CoSi/sub 2//TiSi/sub 2/ for profile analysis 采用RIE处理增强CoSi/sub - 2//TiSi/sub - 2/轮廓的方法进行轮廓分析
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993704
H. Chang, J. Hsieh, J. Horng, C. Lu, H. W. Chang
{"title":"A method of RIE treatment to enhance the contour of CoSi/sub 2//TiSi/sub 2/ for profile analysis","authors":"H. Chang, J. Hsieh, J. Horng, C. Lu, H. W. Chang","doi":"10.1109/ISSM.2000.993704","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993704","url":null,"abstract":"In VLSI technology, CoSi/sub 2//TiSi/sub 2/ configuration is used as a glue layer to reduce contact resistivity. The quality of CoSi/sub 2//TiSi/sub 2/ conformation and remaining of CoSi/sub 2// TiSi/sub 2/ thickness after contact etching process are the key parameters in IC processing. Traditionally, wet etching treatment is usually used to monitor CoSi/sub 2//TiSi/sub 2/ profile. In order to enhance the CoSi/sub 2//TiSi/sub 2/ contour contrast to measure the silicide layer remaining thickness and monitor CoSi/sub 2//TiSi/sub 2/ conformation, wet etching treatment solvent component, concentration and treated time are the major recipe controlling parameters. The other way of silicide profile contrast enhancement is by using dry RIE plasma etching treatment. Compared with wet approach, three items were concluded. First, increasing ion bombardment by decreasing total pressure can produce much clear CoSi/sub 2//TiSi/sub 2/ conformation and contour than wet etching treatment. Second, dry mode has wider etching time window than wet mode. Third, Ar gas only or decreasing CHF/sub 3/ gas flow can get better contrast All of the silicide profiles were checked by SEM.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"57 59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of post N/sub 2/ treatment & USG cap layer to improve tungsten peeling defects for deep sub-micron device yield improvement 优化后N/sub /处理和USG帽层，改善钨剥离缺陷，提高深亚微米器件良率
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993707
Y.L. Cheng, Y. Wang, S.A. Wu, H.L. Wang, J.K. Wang
{"title":"Optimization of post N/sub 2/ treatment & USG cap layer to improve tungsten peeling defects for deep sub-micron device yield improvement","authors":"Y.L. Cheng, Y. Wang, S.A. Wu, H.L. Wang, J.K. Wang","doi":"10.1109/ISSM.2000.993707","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993707","url":null,"abstract":"Integration issue of W-plug peeling from fluorinated silica glass (FSG) in deep sub-micron IMD application was investigated in this study. Tungsten would peel off immediately during post CMP N/sub 2/ treatment in-situ running with USG cap layer deposition after W-plug deposition. Separating or optimizing post-CMP N/sub 2/ treatment and cap layer would solve this peeling issue. The key points of peeling were the bias power of N/sub 2/ treatment and initial USG cap temperature in the HDP-CVD chamber. TOF-SIMS analysis revealed that higher bias power and longer treatment time lead to more fluorine distribution on the USG cap layer surface, which may cause non-Si-F bonding fluorine to react with subsequent Ti/TiN/W metal layer. FTIR spectra also showed that low bias power, adding an extra cooling step before substantial in-situ cap layer deposition or ex-situ cap would increase fluorine stability in FSG/USG interface.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CIM strategy for semiconductor fab-building blocks approach 半导体晶圆厂构建块方法的CIM策略
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993658
G. Baweja, B. OuYang
{"title":"CIM strategy for semiconductor fab-building blocks approach","authors":"G. Baweja, B. OuYang","doi":"10.1109/ISSM.2000.993658","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993658","url":null,"abstract":"The semiconductor manufacturing process is very complicated. The operations are performed on different tools, supplied by different vendors, forcing many semiconductor manufacturers to adopt computer integrated manufacturing (CIM). The challenge in integrating semiconductor-manufacturing environment comes from connectivity and configurability. The CIM strategy for semiconductor fab described in this paper, is developed using building blocks. The building blocks can be seen as a collection of resources-both physical and functional, which can be used individually. These building blocks interact within a loosely coupled framework for task execution, thus allowing the flexibility of adding/changing functionality with minimal impact on the existing system. This is demonstrated by adding various optional building blocks like real-time data acquisition and advanced process control blocks to the CIM application. The base application framework has been used to integrate more than 250 semiconductor manufacturing tools from various vendors at TI semiconductor fab.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Approach to shorten ULSI development lead-time by effective process condition editing and dynamic lot-progress control systems 利用有效的工艺条件编辑和动态批量进度控制系统缩短ULSI开发周期的方法
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993687
H. Ishizuka, H. Takamori, S. Matsumoto, S. Yamaguchi, T. Arakawa
{"title":"Approach to shorten ULSI development lead-time by effective process condition editing and dynamic lot-progress control systems","authors":"H. Ishizuka, H. Takamori, S. Matsumoto, S. Yamaguchi, T. Arakawa","doi":"10.1109/ISSM.2000.993687","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993687","url":null,"abstract":"We have developed a CIM system for ULSI R&D lines, which has the following functions to improve the efficiency in editing process condition such as a process flow and a process recipe; (1) altering a process condition of many trial lots simultaneously, (2) reducing the operation of editing wafer specifications of each process step. Moreover, our CIM system controls dynamically the progress of trial lots by distinguishing two kinds of process steps which operators and engineers take charge of. By our CIM system, the time when an engineer edits the process condition of trial lots has become less than 1/5th in comparison with the previous CIM system.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effective method of reducing slurry for interlayer dielectric CMP 层间介质CMP的有效减浆方法
Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993637
K. Ishimoto
{"title":"The effective method of reducing slurry for interlayer dielectric CMP","authors":"K. Ishimoto","doi":"10.1109/ISSM.2000.993637","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993637","url":null,"abstract":"Recently chemical mechanical polishing (CMP) became a routine process in semiconductor manufacturing process. However one problem is that the slurry consumption in CMP process is very large. Some experiments are aimed at reducing slurry consumption. Our research showed that the slurry was needed only at the start of polishing in ILD CMP and that we could planarize without slurry after the midpoint of polishing. This paper describes a method of reducing slurry for interlayer dielectric CMP and we predict that the application of this method to our ILD CMP process could reduce waste slurry by about 50%.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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