40th Conference Proceedings on Electronic Components and Technology最新文献_第2页

Local CTE mismatch in SM leaded packages: a potential reliability concern SM封装中的本地CTE不匹配:潜在的可靠性问题

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122216

J. Clech, F.M. Langerman, J.A. Augis

引用次数: 27

Flip-chip solder bump fatigue life enhanced by polymer encapsulation 聚合物封装提高倒装片焊点碰撞疲劳寿命

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122212

D. Suryanarayana, R. Hsiao, T. Gall, J. McCreary

{"title":"Flip-chip solder bump fatigue life enhanced by polymer encapsulation","authors":"D. Suryanarayana, R. Hsiao, T. Gall, J. McCreary","doi":"10.1109/ECTC.1990.122212","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122212","url":null,"abstract":"Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin having a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low-CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of resin along an edge of the chip. The encapsulation flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to get consistent flow under the chip without any bubbles is discussed. The filler size distribution and flow under the chip are shown to cross sections of several different materials including low-alpha-emitting encapsulants for memory applications. Novel encapsulant formulations were tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges show a 5 to 10 times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4-joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service-temperature ranges without conventional DNP (distance from neural point) constraints.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126470608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 83

Straddle-board modeling of SMT joint behaviors SMT接头行为跨板建模

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122307

T. Kilinski, D. Goetsch, B. Sandor

引用次数: 2

Computation of transients in lossy VLSI packaging interconnections 损耗VLSI封装互连中瞬态的计算

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122185

J. Liao, O. Palusinski, J. Prince

引用次数: 24

Bare chip test techniques for multichip modules 多芯片模块裸芯片测试技术

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122242

R. Fillion, R. Wojnarowski, W. Daum

引用次数: 15

Parametric shifts in devices: role of packaging variables and some novel solutions 设备参数转换:包装变量的作用和一些新颖的解决方案

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122209

R. Pendse, D. Jennings

{"title":"Parametric shifts in devices: role of packaging variables and some novel solutions","authors":"R. Pendse, D. Jennings","doi":"10.1109/ECTC.1990.122209","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122209","url":null,"abstract":"The resistance-shift phenomena typically encountered in precision analog devices such as operational amplifiers which use the BiFET structure is discussed and resolved. A test chip consisting of fourteen implant resistors acting as piezoelectric strain gauges and temperature-sensing diodes for accurate recording of chip temperature was designed and fabricated. The incremental stressing effect of each packaging operation performed in sequence was measured and characterized using the chip. It was found that the chip-attachment operation results in small residual tensile stress at the chip surface corresponding to positive resistance shifts in the P-type regions of the chip. This stress state prevails in most ceramic packages; however; in plastic packages, severe compressive tractions resulting from the shrinkage of the plastic change the resistance shifts to large negative values for P-type resistors. This clearly limits the merits of low-stress die attach in plastic packages. The merits of some commonly used stress-reduction schemes such as compliant die attach, low-stress encapsulents, and die coatings were assessed. Some novel solutions to package stress, such as thermoplastic die attachment, five-sided coating, and silicon pad, are demonstrated.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115187771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Reliability study of gallium arsenide transistors 砷化镓晶体管可靠性研究

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122261

R. H. Maurer, K. Chao, E. Nhan, R. Benson, C. Bargeron

引用次数: 3

Packaging technology for the NEC SX-3/SX-X Supercomputer NEC SX-3/SX-X超级计算机的封装技术

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122238

D. Akihiro, W. Toshihiko, N. Hideki

引用次数: 40

Design and performance of high-reliability double-layer capacitors 高可靠性双层电容器的设计与性能

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122204

J. Miller, D. Evans

引用次数: 5

A new power cycling technique for accelerated reliability evaluation of plated-through-holes and interconnects in PCBs 一种新的功率循环技术，用于加速pcb板通孔和互连的可靠性评估

40th Conference Proceedings on Electronic Components and Technology Pub Date : 1990-05-20 DOI: 10.1109/ECTC.1990.122225

R. Munikoti, P. Dhar

{"title":"A new power cycling technique for accelerated reliability evaluation of plated-through-holes and interconnects in PCBs","authors":"R. Munikoti, P. Dhar","doi":"10.1109/ECTC.1990.122225","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122225","url":null,"abstract":"A simple PCT (power cycling technique) that can rapidly assess the reliability of copper-plated-through-holes and associated interconnects in complex PCBs (printed circuit boards) has been developed. This PCT has been found to have the ability to quickly discriminate between barrels of good and poor reliability. Failure modes observed in PCT and MIL-T-shock test are identical; thus, a correlation between the two test techniques is valid. For PTH (plated-through-hole) barrels of poor quality, the correlation between the two methods regarding the number of cycles to failure is almost 1:1. This establishes the fact that PCT can, because of its avalanching effect, reliably screen PCBs of inferior quality in a short period of 100-120 cycles (15-20 h). A PCB passing 100-120 PCT cycles consistently passes 100 cycles of MIL-P-55110. The converse is also true. A near 2:1 correlation has been found between PCT and MIL-T-shock for PTH copper barrels of good quality. The design of a standard PCT coupon which will facilitate the use of fixed current levels for given barrel and track resistances and will allow comparison of reliability data from different sources is presented.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125957094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6