{"title":"多芯片模块裸芯片测试技术","authors":"R. Fillion, R. Wojnarowski, W. Daum","doi":"10.1109/ECTC.1990.122242","DOIUrl":null,"url":null,"abstract":"A unique bare-chip test methodology has been developed based upon the GE high-density interconnect (HDI) technology. This methodology allows at-speed testing and screening of complex ASICs (application-specific integrated circuits) and microprocessor chips over the full military temperature range in standard chip-carrier test sockets without any special fixturing or probe cards or in clusters of common chips in a test array. The authors describe the HDI packaging approach and how it is being utilized to perform bare-ship pretest of RAM chips, processors, and complex ASICs and how it can be utilized to provide full preassembly burn-in.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Bare chip test techniques for multichip modules\",\"authors\":\"R. Fillion, R. Wojnarowski, W. Daum\",\"doi\":\"10.1109/ECTC.1990.122242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A unique bare-chip test methodology has been developed based upon the GE high-density interconnect (HDI) technology. This methodology allows at-speed testing and screening of complex ASICs (application-specific integrated circuits) and microprocessor chips over the full military temperature range in standard chip-carrier test sockets without any special fixturing or probe cards or in clusters of common chips in a test array. The authors describe the HDI packaging approach and how it is being utilized to perform bare-ship pretest of RAM chips, processors, and complex ASICs and how it can be utilized to provide full preassembly burn-in.<<ETX>>\",\"PeriodicalId\":102875,\"journal\":{\"name\":\"40th Conference Proceedings on Electronic Components and Technology\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"40th Conference Proceedings on Electronic Components and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.1990.122242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"40th Conference Proceedings on Electronic Components and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1990.122242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A unique bare-chip test methodology has been developed based upon the GE high-density interconnect (HDI) technology. This methodology allows at-speed testing and screening of complex ASICs (application-specific integrated circuits) and microprocessor chips over the full military temperature range in standard chip-carrier test sockets without any special fixturing or probe cards or in clusters of common chips in a test array. The authors describe the HDI packaging approach and how it is being utilized to perform bare-ship pretest of RAM chips, processors, and complex ASICs and how it can be utilized to provide full preassembly burn-in.<>